D12321VF20V Renesas Electronics America, D12321VF20V Datasheet - Page 1194

• Manufacturer Part Number: D12321VF20V
• Description: IC H8S/2321 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix B Internal I/O Registers
SSR0—Serial Status Register 0
Rev.6.00 Sep. 27, 2007 Page 1162 of 1268
REJ09B0220-0600
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
Transmit Data Register Empty
Note: 1. The DMAC is not supported in the H8S/2321.
1
0
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC*
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
:
:
:
R/(W)*
TDRE
7
1
Receive Data Register Full
Note: 1. The DMAC is not supported in the H8S/2321.
0
1
R/(W)*
RDRF
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC*
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
6
0
1
Overrun Error
0
1
or DTC is activated by a TXI interrupt and writes data to TDR
R/(W)*
ORER
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
5
0
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Error Signal Status
0
1
R/(W)*
1
Data has been received normally, and there is no error signal
[Clearing conditions]
• On reset, or in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
Error signal indicating detection of parity error has been sent by receiving device
[Setting condition]
When the error signal is sampled at the low level
ERS
or DTC is activated by an RXI interrupt and reads data from RDR
4
0
Parity Error
0
1
R/(W)*
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
PER
3
0
Note: etu: Elementary time unit (time for transfer of 1 bit)
Transmit End
0
1
TEND
1. The DMAC is not supported in the H8S/2321.
Transmission in progress
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC*
Transmission has ended
[Setting conditions]
• On reset, or in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
R
2
1
writes data to TDR
transmission of a 1-byte serial character when GM = 0 and BLK = 0
transmission of a 1-byte serial character when GM = 0 and BLK = 1
transmission of a 1-byte serial character when GM = 1 and BLK = 0
transmission of a 1-byte serial character when GM = 1 and BLK = 1
Multiprocessor Bit
0
1
MPB
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
R
H'FF7C
1
0
Multiprocessor Bit Transfer
0
1
MPBT
1
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
or DTC is activated by a TXI interrupt and
0
0
Smart Card Interface 0