M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 151

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Table 17.2 Specifications of clock synchronous serial I/O mode (2)
Note 1: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
Note 2: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
1 .
0
Error detection
Select function
C
9
0 .
8 /
B
0
0
0
1
A
8
G
u
7
the UARTi receive interrupt request bit will not change.
selected simultaneously.
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0 -
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1
0
Item
p
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2
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5
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• Overrun error (Note 1)
• CLK polarity selection
• LSB first/MSB first selection
• Continuous receive mode selection
• Transfer clock output from multiple pins selection (UART1) (Note 2)
• Separate CTS/RTS pins (UART0) (Note 2)
• Switching serial data logic (UART2 to UART4)
• TxD, RxD I/O polarity reverse (UART2 to UART4)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
Whether transmission/reception begins with bit 0 or bit 7 can be selected
Reception is enabled simultaneously by a read from the receive buffer register
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
UART0 CTS and RTS pins each can be assigned to separate pins
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
f o
3
2
9
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17. Clock synchronous serial I/O mode
Specification
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