M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 274

MCU 3/5V 0K,PB-FREE 100-QFP

M30800SFP-BL#U5

Manufacturer Part Number
M30800SFP-BL#U5
Description
MCU 3/5V 0K,PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet

Specifications of M30800SFP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SFP-BL#U5M30800SFP-BL#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30800SFP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
1
v
Figure 28.18 V
J
6
1 .
0
C
9
0 .
Memory expansion Mode and Microprocessor Mode (with 3 wait)
BCLK
ALE
CSi
ADi
BHE
RD
BCLK
ALE
CSi
WR,WRL,
WRH
DBi
DB
ADi
BHE
8 /
Read Timing
Write Timing
B
*1:It is a guarantee value with being alone. 55ns.max garantees as t
*2:It depends on operation frequency.
*3:It depends on operation frequency.
0
0
0
1
A
t
t
t
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
t
t
t
t
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
G
8
ac2(RD-DB)
ac2(AD-DB)
d(DB-WR)
h(WR-DB)
h(WR-AD)
h(WR-CS)
w(WR)
u
7
o r
. g
0 -
t
u
d(BCLK-AD)
t
1
d(BCLK-ALE)
0
=(tcyc/2 x n-20)ns.min
t
25ns.max
p
d(BCLK-ALE)
0
25ns.max
, 2
0
t
t
t
=(tcyc x n-40)ns.min
=(tcyc/2-20)ns.min
=(tcyc/2-20)ns.min
=(tcyc/2-20)ns.min
25ns.max
10ns.max
t
d(BCLK-CS)
25ns.max
25ns.max
d(BCLK-AD)
25ns.max
d(BCLK-CS)
d(BCLK-RD)
2
=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
CC
0
tcyc
0
=3V timing diagram (4)
tcyc
5
*1
*1
t
Page 261
h(BCLK-ALE)
t
25ns.max
-2ns.min
t
d(BCLK-WR)
-2ns.min
h(BCLK-ALE)
Hi-Z
t
ac2(AD-DB)
t
t
d(DB-WR) *3
ac2(RD-DB) *2
f o
*2
t
w(WR)
3
2
9
*3
d(BCLK-AD)
Measuring conditions
• V
• Input timing voltage
• Output timing voltage
t
su(DB-BCLK)
40ns.min
+t
CC
:Determined with V
:Determined with V
su(DB-BCLK)
=3V 10%
*1
t
t
t
h(BCLK-WR)
h(WR-CS) *3
h(WR-AD)
t
0ns.min
h(WR-DB)
28. Electrical characteristics
.
*3
t
*3
h(BCLK-AD)
t
t
h(BCLK-RD)
t
t
h(BCLK-CS)
0ns.min
-3ns.min
h(BCLK-AD)
0ns.min
h(BCLK-CS)
0ns.min
0ns.min
t
t
t
0ns.min
h(RD-CS)
h(RD-AD)
h(RD-DB)
0ns.min
0ns.min
IH
OH
=1.5V, V
=1.5V, V
IL
OL
Vcc=3V
=0.5V
=1.5V

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