M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 165

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 19.1 Typical transmit/receive timing in UART mode (compliant with the SIM interface)
1 .
0
C
9
0 .
8 /
B
Transfer Clock
Transmit rnable
bit (TE)
Transmit register
empty flag
(TXEPT)
Transmit interrupt
request bit (IR)
Transfer Clock
Transmit register
empty flag
(TXEPT)
Transmit interrupt
request bit (IR)
Transmit enable
empty flag (TI)
TxDi
RxDi
Signal conductor level
(Note 2)
Receive enable bit
(RE)
RxDi
TxDi
Signal conductor level
(Note 2)
0
0
0
1
A
8
G
u
7
o r
. g
0 -
Shown in () are bit symbols.
The above timing applies to the following settings :
Note 1: After writing to the transfer buffer at above timing, transmission starts at the timing of BRG overflow.
Note 2: Equal in waveform because TxDi and RxDi are connected.
Shown in () are bit symbols.
The above timing applies to the following settings :
u
1
• Parity is enabled.
• One stop bit
• Transmit interrupt cause select bit = "1".
• Parity is enabled.
• One stop bit
• Transmit interrupt cause select bit = "0".
0
p
0
, 2
0
2
0
0
5
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"1
"0
"0
"
"
"
Page 152
19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
Start
ST
ST
ST
ST
Start
bit
bit
f o
D
D
D
D
0
0
0
0
3
D
D
D
D
2
1
1
1
1
9
Tc
Tc
D
D
D
D
2
2
2
2
D
D
D
D
3
3
The level is detected by
the interrupt routine
3
3
D
D
D
D
4
4
4
4
Data is set in the UARTi
transmit buffer register
D
D
D
D
5
5
5
5
D
D
D
D
6
6
6
6
D
D
D
D
7
7
7
7
Parity
Parity
bit
P
P
bit
P
P
SP
SP
SP
SP
Cleared to "0" when interrupt request is accepted, or cleared by software
Cleared to "0" when interrupt request is accepted, or cleared by software
Stop
Stop
bit
bit
Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / f
Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / f
fi : frequency of BRGi rcount source (f
f
n : value set to BRGi
fi : frequency of BRGi rcount source (f
f
n : value set to BRGi
EXT
EXT
Read to receive buffer
: frequency of BRGi rcount source (external clock)
: frequency of BRGi rcount source (external clock)
ST
ST
ST
ST
Transferred from the UARTi transmit buffer
register to the UARTi transmit register
(Note 1)
An "L" level returns from SIM card
due to the occurrence of a parity error
An "L" level returns from TxDi due to
the occurrence of a parity error
D
D
D
D
0
0
0
0
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
EXT
EXT
D
D
D
D
4
4
4
4
1
1
The level is detected by
the interrupt routine
, f
, f
D
D
D
D
8,
8,
5
5
5
5
f
f
32
32
D
D
D
D
)
)
6
6
6
6
Read to receive buffer
D
D
D
D
7
7
7
7
P
P
P
P
SP
SP
SP
SP