M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 308

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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32. Standard serial I/O mode
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1
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0
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The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
leased, which is done when the P5
level. (In the ordinary command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from the factory. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figures 31.1 and 31.3 show the pin connections for the standard serial I/
O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O
switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of
CLK
To use standard serial I/O mode 1 (clock synchronized), set the CLK
The operation uses the four UART1 pins CLK
clock input pin through which an external transfer clock is input. The TxD
RTS
To use standard serial I/O mode 2 (clock asynchronized), set the CLK
reset. The operation uses the two UART1 pins RxD
In the standard serial I/O mode, only the user ROM area indicated in Figure 32.17can be rewritten. The
boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.
9
0 .
8 /
B
0
0
0
1
1
1
A
G
8
pin when the reset is released.
(BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.
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7
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1
0
p
0
, 2
0
2
0
0
5
Page 295
f o
3
2
9
0
(CE) pin is "H" level, the P5
_____
1
, RxD
1
1
, TxD
and TxD
1
and RTS
1
5
.
(EPM) pin "L" level and the CNVss pin "H"
________
1
1
pin to "H" level and release the reset.
(BUSY). The CLK
1
32. Standard serial I/O mode
pin to "L" level and release the
1
pin is for CMOS output. The
1
pin is the transfer