M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 177

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 20.7 The transmission and reception timing in master mode (internal clock)
1 .
0
C
9
0 .
8 /
B
0
0
< Master (Internal Clock) (DINC = 0) >
< Slave (External Clock) (DINC = 1) >
0
1
Data input timing
Master SS input
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
Clock output
(CKPOL=1, CKPH=1)
Data output timing
A
Clock Phase Setting
With bit 1 of UARTi special mode register 3 (addresses 0325
UARTi transmission-reception control register 0 (addresses 032C
combinations of transfer clock phase and polarity can be selected.
Bit 6 of UARTi transmission-reception control register 0 (addresses 032C
sets transfer clock polarity, whereas bit 1 of UARTi special mode register 3 (addresses 0325
02F5
Transfer clock phase and polarity must be the same between the master and slave involved in the
transfer.
Figure 20.7 shows the transmission and reception timing.
• With “0” for bit 1 (CKPH) of UARTi special mode register 3 (addresses 0325
• With “1” for bit 1 (CKPH) of UARTi special mode register 3 (addresses 0325
8
G
u
7
o r
4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level,
the serial transmission start condition is satisfied, though output is indeterminate. After that, serial
transmission is synchronized with the clock. Figure 20.8 shows the timing.
4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level,
the first data is output. After that, serial transmission is synchronized with the clock. Figure 20.9
shows the timing.
. g
0 -
u
1
0
p
16
0
, 2
0
[i = 3 or 4]) sets transfer clock phase.
2
0
0
5
Page 164
"L"
"H"
"H"
"L"
"H"
"L"
"L"
"H"
"H"
"L"
"H"
"L"
f o
3
2
9
D
0
D
1
D
2
20. UARTi Special Mode Register (i = 2 to 4)
D
3
16
D
4
and 02F5
16
and 02FC
D
5
16
16
and 02FC
[i = 3 or 4]) and bit 6 of
16
16
D
6
and 02F5
and 02F5
16
[i = 3 or 4]), four
D
16
7
[i = 3 or 4])
16
16
[i = 3 or
[i = 3 or
16
and