M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 94

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Table 11.1 DMAC specifications
Note: DMA transfer is not effective to any interrupt.
No. of channels
Transfer memory space
Maximum No. of bytes transferred 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
DMA request factors (Note)
Channel priority
Transfer unit
Transfer address direction
Transfer mode
DMA interrupt request generation timing When the transfer counter register changes from "0001
DMA startup
DMA shutdown
Reload timing
Reading / writing the register
Number of DMA transfer cycles
1 .
0
C
9
0 .
8 /
B
0
0
0
1
A
G
8
u
7
o r
. g
0 -
u
1
0
Item
p
0
, 2
0
2
0
0
5
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f o
3
2
forward/fixed (forward direction cannot be specified for both source and
When the transfer counter register changes from "0001
4 (cycle steal method)
• From any address in the 16 Mbytes space to a fixed address (16
• From a fixed address (16 Mbytes space) to any address in the 16 M
Falling edge of INT0 to INT3 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmission and reception interrupt requests
A/D conversion interrupt requests
Software triggers
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority)
8 bits or 16 bits
destination simultaneously)
• Single transfer
• Repeat transfer
• Single transfer
• Repeat transfer
• Single transfer
• Repeat transfer
repeat transfer mode.
Registers are always read/write enabled.
Between SFR and internal RAM : 3 cycles
Between external I/O and external memory : minimum 3 cycles
9
Mbytes space)
bytes space
Transfer ends when the transfer count register is "0000
When the transfer counter is "0000
counter reload register is reloaded into the transfer counter and the
DMA transfer is continued
Transfer starts when DMA transfer count register is more than
"0001
channel i transfer mode select bits
Transfer starts when the DMA is requested after “11
channel i transfer mode select bits
When “00
DMA transfer count register becomes "0000
write
When “00
16
" and the DMA is requested after “01
2
2
” is written to the channel i transfer mode select bits and
” is written to the channel i transfer mode select bits
________
Specification
________
16
", the value in the transfer
16
2
" by DMA transfer or
” is written to the
2
16
” is written to the
16
" to "0000
16
" to "0000
".
11. DMAC
16
16
" in
".