M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 91

• Manufacturer Part Number: M30800SFP-BL#U5
• Description: MCU 3/5V 0K,PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
10. Watchdog Timer
e
E
1
v
J
6
1 .
Figure 10.1 Block diagram of watchdog timer
0
C
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer
interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. Watchdog timer
interrupt is selected when bit 6 of the system control register 0 (address 0008
selected when CM06 is "1". No value other than "1" can be written in CM06. Once when reset is selected
(CM06="1"), watchdog timer interrupt cannot be selected by software.
When X
prescaler division ratio (by 16 or by 128). When X
division by 2 regardless of bit 7 of the watchdog timer control register (address 000F
watchdog timer cycle can be calculated as follows. However, errors can arise in the watchdog timer cycle
due to the prescaler.
When X
When X
For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is
approximately 26.2 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E
watchdog timer interrupt is selected.
The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these
modes and status, counting starts from the value remained before.
In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released. Figure 10.1 shows the block diagram
of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.
9
0 .
8 /
B
0
0
0
1
A
8
G
u
7
o r
. g
0 -
IN
IN
CIN
Watchdog timer cycle =
Watchdog timer cycle =
u
1
Write to the watchdog timer
start register
(address 000E
0
p
is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F
0
is selected in BCLK
, 2
0
is selected in BCLK
2
0
RESET
HOLD
0
BCLK
5
16
Page 78
)
f o
3
2
9
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
Prescaler division ratio (2) x watchdog timer count (32768)
Prescaler
1/128
1/16
1/2
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
CIN
is selected as the BCLK, the prescaler is set for
16
). CM06 is initialized only at reset. After reset,
BCLK
BCLK
Watchdog timer
Set to
“7FFF
16
16
”
:CM06) is "0" and reset is
10. Watchdog Timer
"CM06=0"
Watchdog timer
interrupt request
16
"CM06=1"
Reset
). Therefore, the
16
16
) selects the
) and when