DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet
DF2265TE13V
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DF2265TE13V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2268 Group, 16 H8S/2264 Group Hardware Manual ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of ...
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This LSI is a high-performance microcontroller (MCU) made up of the H8S/2000 CPU with an internal 32-bit configuration as its core, and the peripheral functions required to configure a system. A single-power flash memory (F-ZTAT this LSI's ROM. The F-ZTAT ...
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Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: List of On-Chip Peripheral Functions: Group Name Product Name PC break controller (PBC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer (TMR_0 to TMR_3) ...
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User's Manuals for Development Tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver. 6.01 User's Manual High-performance Embedded Workshop User's Manual Application Notes: Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Document ...
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Rev. 5.00 Sep. 01, 2009 Page viii of l REJ09B0071-0500 ...
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Main Revisions for This Edition Item Page 1.4 Pin Functions 9 Table 1.1 Pin Functions 2.6 Instruction Set 29 Table 2.1 Instruction Classification 2.6.1 Table of 31 Instructions Classified by Function Table 2.3 Data Transfer Instructions 4.8 Usage Note 66 ...
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Item Page 5.6.5 IRQ Interrupt 102 5.6.6 NMI Interrupt 102 Usage Notes 6.3.4 Operation in 107 Transitions to Power- Down Modes 8.2.5 DTC Transfer 119 Count Register A (CRA) 8.5 Operation 127 Figure 8.5 Flowchart of DTC Operation 9.1.1 Port ...
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Item Page 9.2.1 Port 3 Data 151 Direction Register (P3DDR) 9.2.5 Pin Functions 155 • P34/RxD1/SDA0 9.4.1 Port 7 Data 158 Direction Register (P7DDR) 9.6.1 Port F Data 163 Direction Register (PFDDR) Revision (See Manual for Details) Description added P3DDR ...
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Item Page 9.7.1 Port H Data 165 Direction Register (PHDDR) 9.8.1 Port J Data 170 Direction Register (PJDDR) 9.9.1 Port K Data 174 Direction Register (PKDDR) 9.10.1 Port L Data 176 Direction Register (PLDDR) Rev. 5.00 Sep. 01, 2009 Page ...
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Item Page 9.11.1 Port M Data 178 Direction Register (PMDDR) 9.12.1 Port N Data 181 Direction Register (PNDDR) 9.13 Handling of 183 Unused Pins Table 9.3 Examples of Ways to Handle Unused Input Pins 10.3.1 Timer Control 192 Register (TCR) ...
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Item Page 12.2.1 Timer 291 Counter (TCNT) 12.5.7 Notes on 302 Initializing TCNT by Using the TME Bit 13.3.7 Serial Status 320 Register (SSR) 13.3.7 Serial Status 321 Register (SSR) Rev. 5.00 Sep. 01, 2009 Page xiv of l REJ09B0071-0500 ...
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Item Page 13.3.7 Serial Status 322 Register (SSR) 323 Revision (See Manual for Details) Table amended Initial Bit Bit Name Value R/W Description R/( ORER 0 Overrun Error Indicates that an overrun error occurred during reception, causing ...
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Item Page 13.3.7 Serial Status 324 Register (SSR) 14.4.6 Slave 423 Transmit Operation Rev. 5.00 Sep. 01, 2009 Page xvi of l REJ09B0071-0500 Revision (See Manual for Details) Table amended Initial Value Bit Bit Name R/W Description 2 TEND 1 ...
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Item Page 14.4.6 Slave 424 Transmit Operation 15.2 Input/Output Pins 445 Table 15.1 Pin Configuration 15.8.4 Range of 460 Analog Power Supply and Other Pin Settings 20.6.1 Boot Mode 520 Table 20.4 Boot Mode Operation 25.2.2 DC 600 Characteristics Table ...
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Item Page 25.2.2 DC 602 Characteristics Table 25.2 DC Characteristics (2) 603 25.2.4 A/D 615 Conversion Characteristics Table 25.9 A/D Conversion Characteristics 25.3.2 DC 622 Characteristics Table 25.15 DC Characteristics (1) 623 25.3.2 DC 624 Characteristics Table 25.15 DC Characteristics ...
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Item Page 25.3.4 A/D 636 Conversion Characteristics Table 25.22 A/D Conversion Characteristics Appendix B Product 646 to 649Packages amended Codes Revision (See Manual for Details) Table condition amended Condition B (Masked-ROM version 2 5 ...
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All trademarks and registered trademarks are the property of their respective owners. Rev. 5.00 Sep. 01, 2009 Page REJ09B0071-0500 ...
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Section 1 Overview...............................................................................................1 1.1 Features .................................................................................................................................1 1.2 Internal Block Diagram.........................................................................................................3 1.3 Pin Arrangement ...................................................................................................................5 1.4 Pin Functions ........................................................................................................................7 Section 2 CPU..................................................................................................... 13 2.1 Features ...............................................................................................................................13 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ....................................14 2.1.2 Differences from H8/300 CPU ..............................................................................15 ...
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Usage Notes ........................................................................................................................49 2.9.1 TAS Instruction......................................................................................................49 2.9.2 STM/LDM Instruction ...........................................................................................49 2.9.3 Bit Manipulation Instructions ................................................................................49 2.9.4 Access Method for Registers with Write-Only Bits...............................................51 Section 3 MCU Operating Modes ...................................................................... 55 3.1 Operating Mode Selection ..................................................................................................55 3.2 Register Description............................................................................................................56 3.2.1 ...
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Interrupt Exception Handling Vector Table...........................................................84 5.5 Operation.............................................................................................................................88 5.5.1 Interrupt Control Modes and Interrupt Operation ..................................................88 5.5.2 Interrupt Control Mode 0 .......................................................................................92 5.5.3 Interrupt Control Mode 2 (H8S/2268 Group Only) ...............................................94 5.5.4 Interrupt Exception Handling Sequence ................................................................95 5.5.5 Interrupt Response ...
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Section 7 Bus Controller....................................................................................111 7.1 Basic Timing ..................................................................................................................... 111 7.1.1 On-Chip Memory Access Timing (ROM, RAM) ................................................ 111 7.1.2 On-Chip Peripheral Module Access Timing (H'FFFDAC to H'FFFFBF) ........... 112 7.1.3 On-Chip Peripheral Module Access Timing (H'FFFC30 to H'FFFCA3)............. 112 7.2 ...
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Section 9 I/O Ports .............................................................................................139 9.1 Port 1................................................................................................................................. 145 9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 145 9.1.2 Port 1 Data Register (P1DR)................................................................................ 146 9.1.3 Port 1 Register (PORT1)...................................................................................... 146 9.1.4 Pin Functions ....................................................................................................... 147 9.2 Port 3................................................................................................................................. 151 9.2.1 ...
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Port K................................................................................................................................ 173 9.9.1 Port K Data Direction Register (PKDDR) ........................................................... 174 9.9.2 Port K Data Register (PKDR) .............................................................................. 174 9.9.3 Port K Register (PORTK) .................................................................................... 175 9.9.4 Pin Functions ....................................................................................................... 175 9.10 Port L ................................................................................................................................ 176 9.10.1 Port ...
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Buffer Operation (H8S/2268 Group Only) .......................................................... 225 10.5.4 PWM Modes ........................................................................................................ 228 10.5.5 Phase Counting Mode (H8S/2268 Group Only) .................................................. 233 10.6 Interrupt Sources............................................................................................................... 238 10.7 DTC Activation (H8S/2268 Group Only)......................................................................... 239 10.8 A/D Converter Activation ................................................................................................. 239 10.9 ...
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Timing of CMFA and CMFB Setting When a Compare-Match Occurs.............. 270 11.5.3 Timing of Timer Output When a Compare-Match Occurs .................................. 270 11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs .................... 271 11.5.5 TCNT External Reset Timing .............................................................................. ...
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Operation........................................................................................................................... 296 12.3.1 Watchdog Timer Mode ........................................................................................ 296 12.3.2 Interval Timer Mode ............................................................................................ 297 12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 298 12.3.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF) ............................. 298 12.4 Interrupt Sources............................................................................................................... 299 12.5 ...
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Clock.................................................................................................................... 355 13.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 355 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 356 13.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 359 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)................................................................................................................... 361 13.7 ...
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DDC Switch Register (DDCSWR) ...................................................................... 405 14.4 Operation........................................................................................................................... 406 2 14.4 Bus Data Format ............................................................................................ 406 14.4.2 Initial Setting........................................................................................................ 408 14.4.3 Master Transmit Operation .................................................................................. 408 14.4.4 Master Receive Operation.................................................................................... 412 14.4.5 Slave Receive Operation...................................................................................... 417 14.4.6 ...
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Register Description.......................................................................................................... 464 16.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 464 16.3.2 D/A Control Register (DACR) ............................................................................ 465 16.4 Operation........................................................................................................................... 466 16.5 Usage Notes ...................................................................................................................... 467 16.5.1 Analog Power Supply Current in Power-Down Mode......................................... 467 16.5.2 ...
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Input/Output Pins .............................................................................................................. 511 20.5 Register Descriptions ........................................................................................................ 511 20.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 512 20.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 513 20.5.3 Erase Block Register 1 (EBR1) ........................................................................... 514 20.5.4 Erase Block Register 2 (EBR2) ...
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Subclock Waveform Generation Circuit ........................................................................... 549 21.8 Usage Notes ...................................................................................................................... 549 21.8.1 Note on Crystal Resonator ................................................................................... 549 21.8.2 Note on Board Design.......................................................................................... 550 21.8.3 Note on Using a Crystal Resonator...................................................................... 550 Section 22 Power-Down Modes ........................................................................551 22.1 Register ...
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Writing to MSTPCR ............................................................................................ 570 22.11.6 Entering Subactive/Watch Mode and DTC Module Stop (Supported Only by H8S/2268 Group) ................................................................ 570 Section 23 Power Supply Circuit.......................................................................571 23.1 When Internal Power Step-Down Circuit Is Used ............................................................ 571 Section 24 List of ...
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Appendix C Package Dimensions .....................................................................650 Index .........................................................................................................653 Rev. 5.00 Sep. 01, 2009 Page xxxvi of l REJ09B0071-0500 ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2268 Group ......................................................... 3 Figure 1.2 Internal Block Diagram of H8S/2264 Group ......................................................... 4 Figure 1.3 Pin Arrangement of H8S/2268 Group.................................................................... 5 Figure 1.4 Pin Arrangement of H8S/2264 Group.................................................................... 6 Section ...
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Figure 5.6 IWPFn Setting Timing ........................................................................................... 83 Figure 5.7 Block Diagram of Interrupt Control Operation for H8S/2268 Group .................... 89 Figure 5.8 Block Diagram of Interrupt Control Operation for H8S/2264 Group .................... 90 Figure 5.9 Flowchart of Procedure Up to ...
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Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]................. 216 Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]............. 217 Figure 10.6 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR ...
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Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode (H8S/2268 Group Only)......................................................................................... 248 Figure 10.46 Contention between TCNT Write and Clear Operations........................................ 249 Figure 10.47 Contention between TCNT Write and Increment Operations ................................ 249 Figure 10.48 Contention ...
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Section 13 Serial Communication Interface (SCI) Figure 13.1 Block Diagram of SCI_0........................................................................................ 305 Figure 13.2 Block Diagram of SCI_1 or SCI_2 ........................................................................ 306 Figure 13.3 Example of Internal Base Clock when Average Transfer Rate Is Selected (1) ...... 336 Figure ...
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Figure 13.32 Retransfer Operation in SCI Receive Mode ........................................................... 372 Figure 13.33 Example of Reception Processing Flow................................................................. 372 Figure 13.34 Timing for Fixing Clock Output Level................................................................... 373 Figure 13.35 Clock Halt and Restart Procedure .......................................................................... 374 Figure 13.36 Example of ...
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Figure 14.22 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission ....................................................................................................... 435 Figure 14.23 Timing of Stop Condition Issuance........................................................................ 436 Figure 14.24 IRIC Flag Clearance in WAIT = 1 Status .............................................................. 436 Figure 14.25 ICDR Read and ICCR ...
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Section 18 DTMF Generation Circuit Figure 18.1 DTMF Frequencies ................................................................................................ 493 Figure 18.2 DTMF Generation Circuit Diagram ....................................................................... 494 Figure 18.3 TONED Pin Output Equivalent Circuit.................................................................. 497 Figure 18.4 TONED Pin Output Waveform (Row or Column Group Alone) ........................... 497 ...
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Figure 22.3 Software Standby Mode Application Example ...................................................... 564 Figure 22.4 Hardware Standby Mode Timing ........................................................................... 565 Section 23 Power Supply Circuit Figure 23.1 Power Supply Connections When Internal Power Supply Step-Down Circuit Is Used........................................................................................................................ 571 Section 25 Electrical Characteristics ...
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Section 1 Overview Table 1.1 Pin Functions..............................................................................................................7 Section 2 CPU Table 2.1 Instruction Classification..........................................................................................29 Table 2.2 Operation Notation...................................................................................................30 Table 2.3 Data Transfer Instructions ........................................................................................31 Table 2.4 Arithmetic Operations Instructions (1).....................................................................32 Table 2.4 Arithmetic Operations Instructions (2).....................................................................33 Table 2.5 Logic Operations ...
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Table 5.8 Number of States in Interrupt Handling Routine Execution Status..........................98 Table 5.9 Interrupt Source Selection and Clear Control......................................................... 100 Section 8 Data Transfer Controller (DTC) Table 8.1 Activation Source and DTCER Clearing................................................................ 122 Table 8.2 Interrupt Sources, DTC Vector ...
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Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 237 Table 10.24 TPU Interrupts........................................................................................................ 238 Section 11 8-Bit Timers Table 11.1 Pin Configuration ................................................................................................... 259 Table 11.2 8-Bit Timer Interrupt Sources ................................................................................ 274 Table 11.3 Timer Output Priorities .......................................................................................... ...
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Table 14 Bus Timing (with Maximum Influence of t Section 15 A/D Converter Table 15.1 Pin Configuration ................................................................................................... 445 Table 15.2 Analog Input Channels and Corresponding ADDR Registers................................ 446 Table 15.3 A/D Conversion Time (Single Mode) .................................................................... ...
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Table 21.4 External Clock Input Conditions (Duty Adjustment Circuit Not Used)................. 545 Section 22 Power-Down Modes Table 22.1 LSI Internal States in Each Mode........................................................................... 552 Table 22.2 Low Power Dissipation Mode Transition Conditions ............................................ 555 Table 22.3 Oscillation Settling Time ...
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Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture ⎯ Upward-compatible with H8/300 and H8/300H CPUs on an object level ⎯ Sixteen 16-bit general registers ⎯ 65 basic instructions • Various peripheral functions ⎯ Interrupt controller ...
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Section 1 Overview • General I/O ports ⎯ I/O pins: 67 (supported only by the H8S/2268 Group) 51 (supported only by the H8S/2264 Group) ⎯ Input-only pins: 11 • Supports various power-down states • Compact package Code * 2 Package ...
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Internal Block Diagram Figure 1.1 shows the internal block diagram of the H8S/2268 Group and figure 1.2 shows that of the H8S/2264 Group. MD2 MD1 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE P70/TMRI01/TMCI01 P71/TMRI23/TMCI23 P72/TMO0 P73/TMO1 P74/TMO2 P75/TMO3/SCK2 ...
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Section 1 Overview MD2 MD1 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE P70/TMRI01/TMCI01 P71 P72/TMO0 P73/TMO1 P74 P75/SCK2 P76/RxD2 P77/TxD2 P35/SCK1/SCL0 P34/RxD1/SDA0 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 PF3/ADTRG/IRQ3 Figure 1.2 Internal Block Diagram of H8S/2264 Group Rev. 5.00 Sep. 01, ...
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Pin Arrangement Figure 1.3 shows the pin arrangement of the H8S/2268 Group and figure 1.4 shows that of the H8S/2264 Group. P30/TxD0 76 P31/RxD0 77 P32/SCK0/SDA1/IRQ4 78 P33/TxD1/SCL1 79 P34/RxD1/SDA0 80 P35/SCK1/SCL0/IRQ5 81 PF3/ADTRG/IRQ3 ...
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Section 1 Overview P30/TxD0 76 P31/RxD0 77 P32/SCK0/IRQ4 78 79 P33/TxD1 80 P34/RxD1/SDA0 P35/SCK1/SCL0 81 PF3/ADTRG/IRQ3 82 NC PH3/COM4 88 PH2/COM3 89 PH1/COM2 90 PH0/COM1 91 SEG40 92 SEG39 93 SEG38 ...
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Pin Functions Table 1.1 lists the pins functions. Table 1.1 Pin Functions Type Symbol Pin NO. Power Vcc 62 supply CVcc Vss 14 64 Clock XTAL 63 EXTAL 65 OSC1 58 OSC2 ...
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Section 1 Overview Type Symbol Pin NO. RES * 2 System 59 control STBY * 2 61 FWE 66 NMI * 2 Interrupts 60 IRQ5 * 1 81 IRQ4 78 IRQ3 82 IRQ1 40 IRQ0 38 WKP7 ...
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Type Symbol Pin NO. Serial TxD2 68 communi- TxD1 79 cation TxD0 76 Interface RxD2 69 (SCI)/smart RxD1 80 card RxD0 77 interface SCK2 70 SCK1 81 SCK0 78 SCL1 * bus 79 interface * 3 ...
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Section 1 Overview Type Symbol Pin NO. LCD SEG40 100, controller/ SEG 11, driver 13 COM4 COM1 DTMF TONED ...
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Type Symbol Pin NO. PM7 * 1 I/O ports 100 PM6 * 1 1 PM5 * 1 2 PM4 * 1 3 PM3 * 1 4 PM2 * 1 5 PM1 * 1 6 PM0 * 1 7 PN7 to ...
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Section 1 Overview Rev. 5.00 Sep. 01, 2009 Page 12 of 656 REJ09B0071-0500 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU ⎯ 16 × 16-bit register-register multiply: ⎯ 32 ÷ 16-bit register-register divide: • Two CPU operating modes ⎯ Normal mode * ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by a SLEEP instruction ⎯ ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...
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H'0000 Reset exception vector H'0001 H'0002 H'0003 H'0004 (Reserved for system use) H'0005 H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) (a) Subroutine Branch Notes: ...
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Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access is provided to a maximum 16-Mbyte address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC bit extended control register (EXR ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Initial Bit Bit Name Value 1 V Undefined R Undefined R/W 2.4.5 Initial Values of CPU Registers Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR * to ...
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Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 LDM * , STM * ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register ...
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Table 2.3 Data Transfer Instructions Size * 1 Instruction Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Size * Instruction Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L Performs addition or subtraction on data in two general registers SUB immediate data ...
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Table 2.4 Arithmetic Operations Instructions (2) Size * 1 Instruction Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. ...
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Table 2.7 Bit Manipulation Instructions (1) Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the ...
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Table 2.8 Branch Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
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Section 2 CPU Table 2.9 System Control Instructions Size * 1 Instruction Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B else next; ⎯ ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 ...
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Table 2.11 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect 2.7.1 Register ...
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Section 2 CPU 2.7.4 Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @-ERn Register indirect with post-increment⎯@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is ...
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Immediate⎯#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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Section 2 CPU Specified Branch address by @aa:8 (a) Normal Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses ...
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Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Register direct(Rn) Register indirect(@ERn) Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ • Register indirect with pre-decrement @-ERn Effective Address Calculation General register contents General ...
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Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Rev. 5.00 Sep. 01, 2009 Page 46 of 656 REJ09B0071-0500 Effective Address Calculation ...
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Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and ...
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Section 2 CPU Bus-released state * Exception handling state RES = High Reset state * From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be ...
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Usage Notes 2.9.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction ...
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Section 2 CPU The BSET, BCLR, BNOT, BST and BIST instructions are executed as follows: 1. Data is read in bytes. 2. The operation corresponding to the instruction is applied to the specified bit of the data. 3. The byte ...
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The target bit of the data read out is then manipulated. In this example, clearing bit 4 of H'F8 leaves us with H'E8. P17 P16 I/O Output Output P1DDR 1 After bit- 1 manipulation After the bit-manipulation, The data is ...
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Section 2 CPU Write initial data to work area Copy data from work area to register including write-only bit Access data in work area (data-transfer and bit-manipulation instructions can be used) Copy data from work area to register including write-only ...
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P17 P16 I/O Output Output P1DDR 1 RAM0 1 RAM locations are readable and writable, so there is no possibility of a problem if a bit- manipulation instruction is used to clear only bit 4 of RAM0. Read the value ...
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Section 2 CPU Rev. 5.00 Sep. 01, 2009 Page 54 of 656 REJ09B0071-0500 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 and MD1). Only mode 7 can be used in this LSI. ...
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Section 3 MCU Operating Modes 3.2 Register Description The following register is related to the operating mode. • Mode control register (MDCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode. Initial Value Bit Bit Name ⎯ 7 ...
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Address Map Figure 3.1 shows the address map in each operating mode. ROM: 256 kbytes, RAM: 16 kbytes Mode 7 Advanced single-chip mode H'000000 H'03FFFF H'FFB000 H'FFEFBF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 Internal I/O registers H'FFFFC0 H'FFFFFF H8S/2268 ...
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Section 3 MCU Operating Modes H8S/2265 and H8S/2264 ROM: 128 kbytes, RAM: 4 kbytes Mode 7 Advanced single-chip mode H'000000 H'01FFFF H'FFE000 H'FFEFBF H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 Internal I/O registers H'FFFFC0 H'FFFFFF Rev. 5.00 Sep. 01, 2009 Page ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace * , trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved ...
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Exception Source Internal interrupt * 2 External interrupt WKP0 to WKP7 Internal interrupt Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.4.3, Interrupt Exception Handling Vector Table. 3. For details on ...
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Section 4 Exception Handling Figures 4.1 shows an example of the reset sequence. φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents ...
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Traces (Supported Only by the H8S/2268 Group) Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, ...
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Section 4 Exception Handling 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. Note: * Supported only by the ...
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Stack Status after Exception Handling Figures 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP Interrupt control mode 0 Note: 1. Ignored on return 2. Supported only by the H8S/2268 Group. Figure ...
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Section 4 Exception Handling SP SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode advanced ...
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Section 5 Interrupt Controller 5.1 Features This LSI controls interrupts with the interrupt controller. The interrupt controller has the following features: • Two interrupt control modes (H8S/2268 Group only) ⎯ Any of two interrupt control modes can be set by ...
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Section 5 Interrupt Controller INTM1, INTM0 SYSCR NMIEG NMI input IRQ input WKP input Internal interrupt request SWDTEND to TEI2 Interrupt controller Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register IENR1: Interrupt enable register1 ...
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INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR WKP input unit WKP input IWPR Internal interrupt request WOVI0 to TEI2 Interrupt controller Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: ...
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Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ5 * Input IRQ4 Input IRQ3 Input IRQ2 Input IRQ1 Input IRQ0 Input WKP7 Input WKP6 ...
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Register Descriptions The interrupt controller has the following registers. System control register (SYSCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) Interrupt priority register A (IPRA) * ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value ⎯ ⎯ INTM1 0 4 INTM0 0 3 NMIEG 0 ⎯ ⎯ ⎯ Rev. 5.00 Sep. 01, 2009 Page 72 ...
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Interrupt Priority Registers and O (IPRA to IPRG, IPRI to IPRM, IPRO) (H8S/2268 Group Only) The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels for interrupts other ...
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Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQn (H8S/2268 Group H8S/2264 Group 0). Initial Bit Bit Name ...
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IRQ Sense Control Registers H and L (ISCRH and ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQn (H8S/2268 Group H8S/2264 Group ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 7 IRQ3SCB 0 6 IRQ3SCA 0 ⎯ All 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 Rev. 5.00 Sep. 01, 2009 Page 76 of ...
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IRQ Status Register (ISR) ISR indicates the status of IRQn (H8S/2268 Group H8S/2264 Group interrupt requests. Initial Bit Bit Name Value ⎯ All 0 ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 4 IRQ4F 0 3 IRQ3F 0 ⎯ Rev. 5.00 Sep. 01, 2009 Page 78 of 656 REJ09B0071-0500 R/W Description R/( IRQ4 and IRQ3 Flags R/( ...
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Initial Bit Bit Name Value 1 IRQ1F 0 0 IRQ0F 0 Notes the H8S/2268 Group, only 0 can be written to this bit to clear the flag. In the H8S/2264 Group, this bit is readable/writable. 2. Only 0 ...
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Section 5 Interrupt Controller 5.3.6 Wakeup Interrupt Request Register (IWPR) IWPR indicates the status of WKP7 to WKP0 interrupt requests. Initial Bit Bit Name Value 7 IWPF7 0 6 IWPF6 0 5 IWPF5 0 4 IWPF4 0 3 IWPF3 0 ...
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Interrupt Sources 5.4.1 External Interrupts There are 14 external interrupts for the H8S/2268 Group: NMI, IRQ5 to IRQ3, IRQ1, IRQ0, and WKP7 to WKP0, and 13 external interrupts for the H8S/2264 Group: NMI, IRQ4, IRQ3, IRQ1, IRQ0, and WKP7 ...
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Section 5 Interrupt Controller The set timing for IRQnF is shown in figure 5.4. IRQn Input Pin IRQnF Note: H8S/2268 Group H8S/2264 Group The detection of IRQn ...
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Falling edge detection circuit WKP7 Input Falling edge detection circuit WKP6 Input Falling edge detection circuit WKP0 Input Figure 5.5 Block Diagram of Interrupts WKP7 to WKP0 Figure 5.6 shows the IWPFn setting timing. WKPn input IWPFn The vector number ...
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Section 5 Interrupt Controller the corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt request flag is set to 1 when the setting condition is satisfied, regardless of IER settings. Accordingly, refer ...
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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Source Source External Pin NMI IRQ0 IRQ1 Reserved IRQ3 IRQ4 IRQ5 * 3 Reserved DTC * 3 SWDTEND (completion of software initiation data transfer) Watchdog timer 0 ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source TPU channel 1 TGI1A (TGR1A input capture/compare-match) TGI1B (TGR1B input capture/compare-match) TCI1V (overflow 1) TCI1U (underflow 1) * TPU channel 2 TGI2A (TGR2A input capture/compare-match) TGI2B (TGR2B input capture/compare-match) TCI2V ...
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Origin of Interrupt Interrupt Source Source SCI channel 1 ERI1 (receive error 1) RXI1 (receive completion 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) 8-bit timer CMIA2 channel (compare-match A2) CMIB2 (compare-match B2) OVI2 (overflow ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source SCI channel 2 ERI2 (receive error 2) RXI2 (receive completion 2) TXI2 (transmit data empty 2) TEI2 (transmit end 2) Notes: 1. Lower 16 bits of the start address. 2. ...
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Table 5.3 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 ⎯ ⎯ 1 Note: * Supported only by the H8S/2268 Group. Figures 5.7 and 5.8 show block diagrams of the priority ...
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Section 5 Interrupt Controller Interrupt source Figure 5.8 Block Diagram of Interrupt Control Operation for H8S/2264 Group Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.4 shows the interrupts ...
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Default Priority Determination: When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt ...
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Section 5 Interrupt Controller 5.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts, WKP interrupts and on-chip peripheral module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the ...
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Program execution status Interrupt generated Yes IRQ0 Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.9 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Section 5 Interrupt Controller No Yes ...
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Section 5 Interrupt Controller 5.5.3 Interrupt Control Mode 2 (H8S/2268 Group Only) Eight-level masking is implemented for IRQ interrupts, WKP interrupts and on-chip peripheral module interrupts by comparing the interrupt mask level set by bits EXR ...
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Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.5.4 Interrupt Exception Handling Sequence Figure 5.11 shows the interrupt exception handling sequence. The example shown is ...
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Section 5 Interrupt Controller Figure 5.11 Interrupt Exception Handling Rev. 5.00 Sep. 01, 2009 Page 96 of 656 REJ09B0071-0500 ...
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Interrupt Response Times This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.7 shows interrupt response times - the ...
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Section 5 Interrupt Controller Table 5.8 Number of States in Interrupt Handling Routine Execution Status Symbol Instruction fetch S I Branch address read S J Stack manipulation S K Legend: m: Number of wait states in an external device access. ...
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Interrupt request IRQ interrupt Interrupt source clear signal On-chip peripheral module Interrupt controller Figure 5.12 DTC and Interrupt Controller Interrupt controller of DTC control has the following three main functions. Interrupt source selection: For interruption source, select DTC activation request ...
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Section 5 Interrupt Controller Table 5.9 Interrupt Source Selection and Clear Control Settings DTC DTCE DESEL Legend: #: Corresponding interrupt is used. Interrupt source is cleared. (The CPU should clear the source flag in the ...
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Internal address bus Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.13 Contention between Interrupt Generation and Disabling 5.6.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these ...
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Section 5 Interrupt Controller 5.6.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the ...
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Section 6 PC Break Controller (PBC) The H8S/2268 Group includes a PC break controller (PBC), while the H8S/2264 Group does not. The PC break controller (PBC) provides functions that simplify program debugging. Using these functions easy to create ...
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Section 6 PC Break Controller (PBC) BARA Comparator Internal address Access status Comparator BARB Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers. • Break address register A (BARA) • ...
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Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks. Initial Bit Bit Name Value ...
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Section 6 PC Break Controller (PBC) Initial Bit Bit Name Value 0 BIEA 0 Notes: 1. Only a 0 can be written to this bit to clear the flag. 2. Read the state wherein CMFA = 1 twice or more, ...
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PC Break Interrupt Due to Data Access 1. Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack ...
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Section 6 PC Break Controller (PBC) After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D)). SLEEP ...
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Usage Notes 6.4.1 Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. ...
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Section 6 PC Break Controller (PBC) 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction When the I bit is set by an LDC, ANDC, ORC, or XORC instruction break interrupt becomes valid two states after ...
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Section 7 Bus Controller The H8S/2000 CPU is driven by a system clock, denoted by the symbol φ. The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip peripheral ...
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Section 7 Bus Controller 7.1.2 On-Chip Peripheral Module Access Timing (H'FFFDAC to H'FFFFBF) Addresses H'FFFDAC to H'FFFFBF in the on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on ...
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Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Figure 7.3 On-Chip Peripheral Module Access Cycle (H'FFFC30 to H'FFFCA3) 7.2 Bus Arbitration (H8S/2268 Group Only) The Bus Controller has ...
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Section 7 Bus Controller 7.2.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus ...
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Section 8 Data Transfer Controller (DTC) The H8S/2268 Group includes a data transfer controller (DTC), while the H8S/2264 Group does not. The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram ...
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Section 8 Data Transfer Controller (DTC) Interrupt controller Interrupt request CPU interrupt request Legend: MRA, MRB: DTC mode registers A and B CRA, CRB: DTC transfer count registers A and B SAR: DTC source address register DAR: DTC destination address ...
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When activated, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. ...
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Section 8 Data Transfer Controller (DTC) Initial Bit Bit Name Value Undefined ⎯ 1 DTS Undefined ⎯ Legend: X: Don’t care 8.2.2 DTC Mode Register B (MRB) MRB is an 8-bit register that selects the DTC operating mode. ...
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Initial Bit Bit Name Value ⎯ Undefined ⎯ 8.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an ...
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Section 8 Data Transfer Controller (DTC) 8.2.7 DTC Enable Register (DTCER) DTCER is comprised of seven registers; DTCERA to DTCERF and DTCERI, and is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits ...
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DTC Vector Register (DTVECR) DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Initial Bit Bit Name Value 7 SWDTE 0 6 DTVEC6 0 ...
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Section 8 Data Transfer Controller (DTC) 8.3 Activation Sources The DTC operates when activated by an interrupt write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the ...
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Source flag cleared On-chip peripheral module IRQ interrupt Interrupt request DTVECR Figure 8.2 Block Diagram of DTC Activation Source Control 8.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to ...
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Section 8 Data Transfer Controller (DTC) Register MRA information start address Chain transfer MRA Figure 8.3 The Location of DTC Register Information in Address Space DTC vector address Figure 8.4 Correspondence between DTC Vector Address and Register Information Rev. 5.00 ...
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Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Origin of Interrupt Source Source Software Write to DTVECR External pin IRQ0 IRQ1 IRQ3 IRQ4 IRQ5 A/D ADI (A/D conversion end) TPU TGI0A Channel 0 TGI0B TGI0C TGI0D TPU ...
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Section 8 Data Transfer Controller (DTC) Interrupt Origin of Interrupt Source Source IIC channel 0 IICI0 IIC channel 1 IICI1 SCI RXI2 channel 2 TXI2 Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with ...
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Read register infomation Write register information Transfer Counter = 0 Clear an activeation flag Note: * For details, see section related to each peripheral module. Figure 8.5 Flowchart of DTC Operation 8.5.1 Normal Mode In normal mode, one operation transfers ...
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Section 8 Data Transfer Controller (DTC) Table 8.3 Register Information in Normal Mode Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B SAR Figure 8.6 Memory Mapping in Normal Mode ...
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Table 8.4 Register Information in Repeat Mode Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B SAR Repeat area or DAR Figure 8.7 Memory Mapping ...
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Section 8 Data Transfer Controller (DTC) Table 8.5 Register Information in Block Transfer Mode Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B First block ...
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Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can ...
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Section 8 Data Transfer Controller (DTC) 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers data transfer for which the DISEL bit was set to 1. ...
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DTC activation request DTC request Vector read Address Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, φ DTC activation request DTC request Vector read Address Figure 8.12 DTC Operation Timing (Example of Chain Transfer) Section 8 Data ...
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Section 8 Data Transfer Controller (DTC) 8.5.7 Number of DTC Execution States Table 8.6 lists execution status for a single DTC data transfer, and table 8.7 shows the number of states required for each execution status. Table 8.6 DTC Execution ...
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Number of execution states = I · S For example, when the DTC vector address table is located in the on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the ...
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Section 8 Data Transfer Controller (DTC) 8.7 Examples of Use of DTC 8.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed ...
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Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60 not, this indicates ...
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Section 8 Data Transfer Controller (DTC) Rev. 5.00 Sep. 01, 2009 Page 138 of 656 REJ09B0071-0500 ...
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The H8S/2268 Group has ten I/O ports (ports and J to N), and two input-only port (ports 4 and 9). The H8S/2264 Group has eight I/O ports (ports and J ...
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Section 9 I/O Ports Table 9.1 H8S/2268 Group Port Functions (1) Port Description Port 1 General I/O port also functioning as TPU I/O pins and interrupt input pins Port 3 General I/O port also functioning as SCI_0 and SCI_1 I/O ...
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Port Description Port 9 General input port also functioning as A/D converter analog input and D/A converter analog output pins Port F General I/O port also functioning as interrupt input pins and an A/D converter input pins Port H General ...
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Section 9 I/O Ports Port Description Port L General I/O port also functioning as LCD segment output pins Port M General I/O port also functioning as LCD segment output pins Port N General I/O port also functioning as LCD segment ...
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Table 9.1 H8S/2264 Group Port Functions (2) Port Description Port 1 General I/O port also functioning as TPU I/O pins and interrupt input pins Port 3 General I/O port also functioning as SCI_0 and SCI_1 I/O pins, I bus interface ...
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Section 9 I/O Ports Port Description Port 9 General input port also functioning as A/D converter analog inputs Port F General I/O port also functioning as interrupt input pins and an A/D converter input pins Port H General input port ...
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Port Description Port L General I/O port also functioning as LCD segment output pins 9.1 Port 1 Port 8-bit I/O port and has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data ...
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Section 9 I/O Ports Initial Bit Bit Name Value 7 P17DDR 0 6 P16DDR 0 5 P15DDR 0 4 P14DDR 0 3 P13DDR 0 2 P12DDR 0 1 P11DDR 0 0 P10DDR 0 9.1.2 Port 1 Data Register (P1DR) P1DR ...
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Initial Bit Bit Name Value ⎯* 7 P17 ⎯* 6 P16 ⎯* 5 P15 ⎯* 4 P14 ⎯* 3 P13 ⎯* 2 P12 ⎯* 1 P11 ⎯* 0 P10 Note: * Determined by the states of pins P17 to P10. ...
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Section 9 I/O Ports • P16/TIOCA2/IRQ1 The pin function is switched as shown below according to the combination of the TPU channel 2 setting and the P16DDR bit. TPU Channel 2 Setting P16DDR Pin function Notes: 1. This pin functions ...