DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 17

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
13.3.7 Serial Status
Register (SSR)
Page
322
323
Revision (See Manual for Details)
Table amended
Table amended
Bit
5
4
Bit
3
Bit Name
ORER
ERS
Bit Name
PER
Initial
Value
0
0
Initial
Value
0
R/W
R/(W) *
R/(W) *
R/W
R/(W) *
1
1
1
Description
Overrun Error
Indicates that an overrun error occurred during reception,
causing abnormal termination.
[Setting condition]
When the next serial reception is completed while RDRF
= 1
The receive data prior to the overrun error is retained in
RDR, and the data received subsequently is lost. Also,
subsequent serial cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
The ORER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
Error Signal Status
Indicates that the status of an error, signal 1 returned from
the reception side at reception
[Setting condition]
When the low level of the error signal is sampled
[Clearing condition]
When 0 is written to ERS after reading ERS = 1
The ERS flag is not affected and retains its previous state
when the RE bit in SCR is cleared to 0.
Description
Parity Error
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent serial
reception cannot be continued while the PER flag is set to
1. In clocked synchronous mode, serial transmission
cannot be continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its previous state
when the RE bit in SCR is cleared to 0.
Rev. 5.00 Sep. 01, 2009 Page xv of l
REJ09B0071-0500