DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 439

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3
The I
and SAR are allocated to the same addresses. Accessible addresses differ depending on the ICE bit
in ICCR. SAR and SARX are accessed when ICE is 0, and ICMR and ICDR are accessed when
ICE is 1. For details on the module stop control register, refer to section 22.1.2, Module Stop
Control Registers A to D (MSTPCRA to MSTPCRD).
• I
• Slave address register_0 (SAR_0) *
• Second slave address register_0 (SARX_0) *
• I
• I
• I
• I
• Slave address register_1 (SAR_1) *
• Second slave address register_1 (SARX_1) *
• I
• I
• I
• DDC switch register (DDCSWR)
• Serial control register X (SCRX)
Notes: 1. Supported only by the H8S/2268 Group.
2
2
2
2
2
2
2
2
C bus data register_0 (ICDR_0) *
C bus mode register_0 (ICMR_0) *
C bus control register_0 (ICCR_0) *
C bus status register_0 (ICSR_0) *
C bus data register_1 (ICDR_1) *
C bus mode register_1 (ICMR_1) *
C bus control register_1 (ICCR_1) *
C bus status register_1 (ICSR_1) *
2
C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
2. Some of the registers in the I
Register Descriptions
other registers. The IICE bit in serial control register X (SCRX) selects each register.
Section 14 I
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
2
1
2
1
*
2
1
*
2
1
2
*
2
C bus interface are allocated to the same addresses of
2
2
*
1
2
*
2
2
2
1
*
2
Rev. 5.00 Sep. 01, 2009 Page 387 of 656
REJ09B0071-0500