DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 502

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 A/D Converter
15.4
ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus
master accesses to the upper byte of the registers directly while to the lower byte of the registers
via the temporary register (TEMP).
Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data
will be transferred to the CPU and the lower-byte data will be transferred to TEMP. Then, when
the lower-byte data is read, the lower-byte data will be transferred to the CPU.
When data in ADDR is read, the data should be read from the upper byte and lower byte in the
order. When only the upper-byte data is read, the data is guaranteed. However, when only the
lower-byte data is read, the data is not guaranteed.
Figure 15.2 shows data flow when accessing to ADDR.
Rev. 5.00 Sep. 01, 2009 Page 450 of 656
REJ09B0071-0500
Bus master
Bus master
(H'AA)
(H'40)
Interface to Bus Master
Read the upper byte
Read the lower byte
Figure 15.2 Access to ADDR (When Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
Module data bus
ADDRnL
Module data bus
ADDRnL
TEMP
TEMP
(H'40)
(H'40)
(H'40)
(H'40)
(n = A to D)
(n = A to D)