DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 170

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
Legend:
X: Don’t care
8.2.2
MRB is an 8-bit register that selects the DTC operating mode.
Rev. 5.00 Sep. 01, 2009 Page 118 of 656
REJ09B0071-0500
Bit
1
0
Bit
7
6
Bit Name
DTS
Sz
Bit Name
CHNE
DISEL
DTC Mode Register B (MRB)
Initial
Value
Undefined ⎯
Undefined ⎯
Initial
Value
Undefined ⎯
Undefined ⎯
R/W
R/W
Description
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Description
DTC Chain Transfer Enable
This bit specifies a chain transfer. For details, refer to
8.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing of
the interrupt source flag, and clearing of DTCER, are
not performed.
0: DTC data transfer completed (waiting for start)
1: DTC data transfer (reads new register information
DTC Interrupt Select
This bit specifies whether CPU interrupt is disabled or
enabled after a data transfer.
0: Interrupt request is issued to the CPU when the
1: DTC issues interrupt request to the CPU in every
and transfers data)
specified data transfer is completed.
data transfer (DTC does not clear the interrupt
request flag that is a cause of the activation).