MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 293

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.13.6 MSCAN08 Receiver Interrupt Enable Register
WUPIE — Wakeup Interrupt Enable
RWRNIE — Receiver Warning Interrupt Enable
TWRNIE — Transmitter Warning Interrupt Enable
RERRIE — Receiver Error Passive Interrupt Enable
TERRIE — Transmitter Error Passive Interrupt Enable
BOFFIE — Bus-Off Interrupt Enable
OVRIE — Overrun Interrupt Enable
RXFIE — Receiver Full Interrupt Enable
Freescale Semiconductor
1 = A wakeup event will result in a wakeup interrupt.
0 = No interrupt will be generated from this event.
1 = A receiver warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receiver error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A bus-off event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = An overrun event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event will result in a receive interrupt.
0 = No interrupt will be generated from this event.
Address:
The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Figure 23-20. Receiver Interrupt Enable Register (CRIER)
WUPIE
$0505
Bit 7
0
RWRNIE
6
0
TWRNIE
5
0
NOTE
RERRIE
4
0
TERRIE
3
0
Programmer’s Model of Control Registers
BOFFIE
2
0
OVRIE
1
0
RXFIE
Bit 0
0
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