HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 126

• Manufacturer Part Number: HD6473228F10V
• Description: MCU 5V 32K,PB-FREE 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473228F10V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

Bit 6—Input Strobe Interrupt Enable (ISIE): Enables or disables the handshake interrupt
request (ISI).
Bit 6
ISIE
0
1
Bit 5—Output Strobe Enable (OSE): Enables or disables output of the output strobe signal. Do
not set OSE to 1 in the expanded modes (modes 1 and 2).
Bit 5
OSE
0
1
Bit 4—Output Strobe Select (OSS): Selects whether to generate an output strobe signal when the
port 3 data register (P3DR) is written, or when it is read.
Bit 4
OSS
0
1
Bit 3—Latch Enable (LTE): Controls the input latches of port 3. Do not set LTE to 1 in the
expanded modes (modes 1 and 2).
When LTE is set to 1, input data are latched on the falling edge of IS. The data are retained in the
input latch until the port 3 data register (P3DR) is read, after which the next data can be latched.
Bit 3
LTE
0
1
Description
The handshake interrupt request (ISI) is disabled.
The handshake interrupt request (ISI) is enabled.
Description
The output strobe signal is disabled.
The output strobe signal is enabled.
Description
An output strobe signal is output when P3DR is read.
An output strobe signal is output when P3DR is written.
Description
Port 3 input data are not latched.
Port 3 input data are latched on the falling edge of IS.
117
(Initial value)
(Initial value)
(Initial value)
(Initial value)