HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 70

• Manufacturer Part Number: HD6473228F10V
• Description: MCU 5V 32K,PB-FREE 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473228F10V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

4.1 Overview
The H8/325 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1
indicates their priority and the timing of their hardware exception-handling sequence. The ROMless
versions (HD6413258, HD6413238) are used only in mode 1 (expanded mode with on-chip ROM
disabled).
Table 4-1. Reset and Interrupt Exceptions
Priority
High
Low
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the RES pin goes low, all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. When RES returns from low to high, the chip
comes out of the reset state via the reset exception-handling sequence.
4.2.2 Reset Sequence
The reset state begins when RES goes low. To ensure correct resetting, at power-on the RES pin
should be held low for at least 20ms. In a reset during operation, the RES pin should be held low
for at least 10 system clock (Ø) cycles.
When RES returns from low to high, hardware carries out the following reset exception-handling
sequence.
Type of
exception
Reset
Interrupt
Section 4. Exception Handling
Timing of exception-handling sequence
When RES goes low, the chip enters the reset state immediately. The
hardware exception-handling sequence (reset sequence) begins as
soon as RES goes high again.
When an interrupt is requested, the hardware exception-handling
sequence (interrupt sequence) begins at the end of the current
instruction, or at the end of the current hardware exception-handling
sequence.
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