HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 79

• Manufacturer Part Number: HD6473228F10V
• Description: MCU 5V 32K,PB-FREE 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473228F10V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

Note: Interrupt requests are not detected immediately after the ANDC, ORC, XORC, and LDC
instructions.
4.3.5 Interrupt Handling
Figure 4-3 shows a block diagram of the interrupt controller. Figure 4-4 is a flowchart showing the
operation of the interrupt controller and the sequence by which an interrupt is accepted. This
sequence is outlined below.
(1) The interrupt controller receives an interrupt request signal. Interrupt request signals can be
(2) When notified of an interrupt, the interrupt controller scans the interrupt signals in priority
(3) The interrupt controller accepts the interrupt if it is an NMI, or if it is another interrupt and the
(4) When an interrupt is accepted, after completion of the current instruction, first the PC then the
(5) The interrupt controller sets the I bit in the CCR to 1, masking all further interrupts except
(6) The interrupt controller generates the vector address of the interrupt and loads the word at this
generated by NMI input, or by other interrupt sources if enabled.
order and selects the one with the highest priority. (See table 4-2 for the priority order.) Other
requested interrupts remain pending.
I bit in the CCR is cleared to 0. If the interrupt is not an NMI and the I bit is set to 1, the
interrupt is held pending.
CCR is pushed onto the stack. See figure 4-5. The stacked PC indicates the address of first
instruction executed after return from the interrupt-handling routine.
NMI during the interrupt-handling routine.
address into the program counter.
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