HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 135

MCU 5V 32K,PB-FREE 64-QFP

HD6473228F10V

Manufacturer Part Number
HD6473228F10V
Description
MCU 5V 32K,PB-FREE 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet

Specifications of HD6473228F10V

Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473228F10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TCR) is set to 1, when the output compare register and FRC values match, the logic level selected
by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin
(FTOA or FTOB).
Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used for write
access, as explained in section 7.3, CPU Interface.
OCRA and OCRB are initialized to H’FFFF at a reset and in the standby modes.
7.2.3 Input Capture Register (ICR) – H’FF98
Bit
Initial 0
value
Read/ R
Write
The input capture register is a 16-bit read-only register.
When the rising or falling edge of the signal at the input capture pin (FTI) is detected, the current
value of the FRC is copied to the input capture register (ICR). At the same time, the input capture
flag (ICF) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected
by the input edge select bit (IEDG) in the TCSR.
Because the input capture register is a 16-bit register, a temporary register (TEMP) is used when it
is read. See Section 7.3, CPU Interface for details.
To ensure input capture, when the noise canceler is not used, the width of the input capture pulse
(FTI) should be at least 1.5 system clock cycles (1.5·Ø).
15
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
R
9
0
127
R
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0

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