HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 200

• Manufacturer Part Number: HD6473228F10V
• Description: MCU 5V 32K,PB-FREE 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473228F10V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

Table 9-9. SCI Interrupts
Interrupt
ERI
RXI
TXI
9.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is 0, before the old TDR contents
have been moved into the TSR, the old byte will be lost. Normally, software should check that the
TDRE bit is set to 1 before writing to the TDR.
(2) Multiple Receive Errors: Table 9-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
Table 9-10. SSR Bit States and Data Transfer When Multiple Receive Errors Occur
Receive error
Overrun error
Framing error
Parity error
Overrun + framing errors
Overrun + parity errors
Framing + parity errors
Overrun + framing + parity errors
*
*
1
2
Set to 1 before the overrun error occurs.
Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
Description
Receive-error interrupt, requested when ORER, FER, or PER
is set. RIE must also be set.
Receive-end interrupt, requested when RDRF and RIE are set.
Transmit-end interrupt, requested when TDRE and TIE are set.
RDRF
1*
0
0
1*
1*
0
1*
1
1
1
1
193
SSR Bits
ORER
1
0
0
1
1
0
1
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
Priority
High
Low
RSR
No
Yes
Yes
No
No
Yes
No
RDR*
2