HD6473228F10V Renesas Electronics America, HD6473228F10V Datasheet - Page 127

MCU 5V 32K,PB-FREE 64-QFP

HD6473228F10V

Manufacturer Part Number
HD6473228F10V
Description
MCU 5V 32K,PB-FREE 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheet

Specifications of HD6473228F10V

Core Processor
H8/300
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473228F10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 2—Busy Enable (BSE): This bit enables or disables output of the busy signal. Do not set BSE
to 1 in the expanded modes (modes 1 and 2).
Bit 2
ISIE
0
1
Bits 1 and 0—Reserved: These bits cannot be modified and are always read as 1.
6.3 Operation
6.3.1 Output Timing of Output Strobe Signal
The output strobe signal is output when the port 3 data register (P3DR) is written or read. The
output strobe signal goes low at the seventh system clock cycle after P3DR is written or read,
remains low for eight system clock cycles, then goes high. Figure 6-2 shows how the output strobe
signal is output after P3DR is written (when OSS = 1).
Note the following point when reading or writing P3DR twice consecutively.
If P3DR is written or read once, then written or read again within 15 states, the output strobe signal
is not output for the second write or read. Figure 6-3 shows an example of this when OSS = 1.
Port 3
Ø
OS
Description
Busy signal output is disabled.
Busy signal output is enabled.
Port 3 write
Figure 6-2. Output Strobe Output Timing (When OSS = 1)
7 system clocks
8 system clocks
118
(Initial value)

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