HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 178

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Control of Insertion of Wait States Using the WAIT
states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When
the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends
in 1 state and no wait states are inserted. When the bit is 1, the WAIT pin input signal is sampled
on the rise of the system clock (CK) directly preceding the second state of the column address
output cycle and the wait state is inserted as long as the level is low. When a high level is detected,
it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle.
Rev. 7.00 Jan 31, 2006 page 150 of 658
REJ09B0272-0700
A21–A0
A21–A0
WAIT
RAS
CAS
RAS
CAS
CK
CK
Figure 8.20 Wait State Timing during DRAM Access (Long Pitch)
T
T
p
p
1
Figure 8.19 Precharge Timing (Long Pitch)
Row address
T
T
p
r
2
T
Row address
WAIT
WAIT
WAIT Pin Input Signal: The number of wait
T
c
r
1
T
cw
Column address
(wait state)
T
c
1
Column address
T
T
c
c
2
2