HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 376

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
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Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Section 12 Watchdog Timer (WDT)
12.3.2
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer
interrupt (ITI) is generated each time the timer counter overflows. This function can be used to
generate interval timer interrupts at regular intervals (figure 12.5).
12.3.3
The watchdog timer has a special function to clear standby mode with an NMI interrupt. When
using standby mode, set the WDT as described below.
Transition to Standby Mode: The TME bit in TCSR must be cleared to 0 to stop the watchdog
timer counter before it enters standby mode. The chip cannot enter standby mode while the TME
bit is set to 1. Set bits CKS2–CKS0 so that the counter overflow interval is equal to or longer than
the oscillation settling time. See sections 20.1.3 and 20.2.3, AC Characteristics, for the oscillation
settling time.
Recovery from Standby Mode: When an NMI request signal is received in standby mode, the
clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits
CKS2–CKS0 before standby mode was entered. When TCNT overflows (changes from H'FF to
H'00), the system clock ( ) is presumed to be stable and usable; clock signals are supplied to the
entire chip and standby mode ends.
For details on standby mode, see section 19, Power Down State.
Rev. 7.00 Jan 31, 2006 page 348 of 658
REJ09B0272-0700
H'FF
H'00
ITI: Interval timer interrupt request
TCNT value
WT/IT = 0
Operation in Interval Timer Mode
Operation in Standby Mode
TME = 1
Figure 12.5 Operation in Interval Timer Mode
Overflow
ITI
Overflow
ITI
Overflow
ITI
Overflow
ITI
Time

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