HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 611

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
A.2.15
Start Address: H'5FFFF05 (channel 0), H'5FFFF0F (channel 1), H'5FFFF19 (channel 2),
H'5FFFF23 (channel 3), H'5FFFF33 (channel 4)
Bus Width: 8
Bit
Initial value
Read/Write
Note: * Undetermined
Table A.16 TIO0–TIO4 Bit Functions
Bit
2–0
Note: * 0 or 1
6–4 I/O control B2–0
Bit name
(IOB2–IOB0)
I/O control A2–0
(IOA2–IOA0)
Timer I/O Control Registers 0–4 (TIOR0–TIOR4)
7
*
Value
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
IOB2
R/W
0
1
0
1
0
1
*
0
1
0
1
0
1
*
6
0
Description
GRB is output
compare register
GRB is input
capture register
GRA is output
compare register
GRA is input
capture register
IOB1
R/W
5
0
Appendix A On-Chip Supporting Module Registers
IOB0
R/W
4
0
Pin output due to compare match
disabled
0 output on GRB compare match
1 output on GRB compare match
Toggle output on GRB compare match
(1 output on channel 2 only)
Input capture to GRB on rising edge
Input capture to GRB on falling edge
Input capture on both rising and falling
edges
Pin output due to compare match
disabled
0 output on GRA compare match
1 output on GRA compare match
Toggle output on GRA compare match
(1 output on channel 2 only)
Input capture to GRA on rising edge
Input capture to GRA on falling edge
Input capture on both rising and falling
edges
Rev. 7.00 Jan 31, 2006 page 583 of 658
3
1
IOA2
R/W
2
0
REJ09B0272-0700
IOA1
R/W
1
0
(Initial value)
(Initial value)
IOA0
R/W
0
0
ITU

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