HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 27

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

A.3
Appendix B Pin States
Appendix C Package Dimensions
A.2.50 Timer Control/Status Register (TCSR) WDT...................................................... 621
A.2.51 Timer Counter (TCNT) WDT.............................................................................. 623
A.2.52 Reset Control/Status Register (RSTCSR) WDT .................................................. 623
A.2.53 Standby Control Register (SBYCR) Power-Down State ..................................... 624
A.2.54 Port A Data Register (PADR) Port A .................................................................. 625
A.2.55 Port B Data Register (PBDR) Port B ................................................................... 626
A.2.56 Port C Data Register (PCDR) Port C ................................................................... 627
A.2.57 Port A I/O Register (PAIOR) PFC....................................................................... 628
A.2.58 Port B I/O Register (PBIOR) PFC ....................................................................... 629
A.2.59 Port A Control Register 1 (PACR1) PFC............................................................. 630
A.2.60 Port A Control Register 2 (PACR2) PFC............................................................. 632
A.2.61 Port B Control Register 1 (PBCR1) PFC ............................................................. 634
A.2.62 Port B Control Register 2 (PBCR2) PFC ............................................................. 636
A.2.63 Column Address Strobe Pin Control Register (CASCR) PFC............................. 638
A.2.64 TPC Output Mode Register (TPMR) TPC........................................................... 639
A.2.65 TPC Output Control Register (TPCR) TPC......................................................... 640
A.2.66 Next Data Enable Register A (NDERA) TPC ..................................................... 642
A.2.67 Next Data Enable Register B (NDERB) TPC...................................................... 642
A.2.68 Next Data Register A (NDRA) TPC
A.2.69 Next Data Register A (NDRA) TPC
A.2.70 Next Data Register A (NDRA) TPC
A.2.71 Next Data Register A (NDRA) TPC
A.2.72 Next Data Register B (NDRB) TPC
A.2.73 Next Data Register B (NDRB) TPC
A.2.74 Next Data Register B (NDRB) TPC
A.2.75 Next Data Register B (NDRB) TPC
Register Status in Reset and Power-Down States ............................................................. 647
(When the Output Triggers of TPC Output Groups 0 and 1 are the Same).......... 643
(When the Output Triggers of TPC Output Groups 0 and 1 are the Same).......... 643
(When the Output Triggers of TPC Output Groups 0 and 1 are Different).......... 644
(When the Output Triggers of TPC Output Groups 0 and 1 are Different).......... 644
(When the Output Triggers of TPC Output Groups 2 and 3 are the Same).......... 645
(When the Output Triggers of TPC Output Groups 2 and 3 are the Same).......... 645
(When the Output Triggers of TPC Output Groups 2 and 3 are Different).......... 646
(When the Output Triggers of TPC Output Groups 2 and 3 are Different).......... 647
....................................................................................................... 650
................................................................................... 656
Rev. 7.00 Jan 31, 2006 page xxv of xxvi