HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 472

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 15 Pin Function Controller (PFC)
Bits 1 and 0—PB0 Mode (PB0MD1 and PB0MD0): PB0MD1 and PB0MD0 select the function
of the PB0/TP0/TIOCA2 pin.
Bit 1:
PB0MD1
0
1
15.3.5
CASCR is a 16-bit read/write register that allows selection between column address strobe and
chip select pin functions. CASCR is initialized to H'5FFF by a power-on reset, but is not
initialized by a manual reset, or in standby mode or sleep mode.
Bits 15 and 14—CASH Mode (CASHMD1 and CASHMD0): CASHMD1 and CASHMD0
select the function of the CS1/CASH pin.
Bit 15:
CASHMD1
0
1
Rev. 7.00 Jan 31, 2006 page 444 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Column Address Strobe Pin Control Register (CASCR)
Bit 14:
CASHMD0
0
1
0
1
Bit 0:
PB0MD0
0
1
0
1
CASH
MD1
R/W
15
—
—
0
7
1
Function
Input/output (PB0)
Reserved
ITU input capture/output compare (TIOCA2)
Timing pattern output (TP0)
Function
Reserved
Chip select output (CS1)
Column address strobe output (CASH)
Reserved
CASH
MD0
R/W
14
—
—
1
6
1
CASL
MD1
R/W
13
—
—
0
5
1
CASL
MD0
R/W
12
—
—
1
4
1
11
—
—
—
—
1
3
1
10
—
—
—
—
1
2
1
—
—
—
—
9
1
1
1
(Initial value)
(Initial value)
—
—
—
—
8
1
0
1