HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 274

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1 and CCLR0): CCLR1 and CCLR0 select the
counter clear source.
Bit 6:
CCLR1
0
1
Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a
Bits 4 and 3—External Clock Edge 1/0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select
external clock input edge. When channel 2 is set for phase counting mode, settings of the CKEG1
and CKEG0 bits in TCR are ignored and the phase counting mode operation takes priority.
Bit 4:
CKEG1
0
1
Rev. 7.00 Jan 31, 2006 page 246 of 658
REJ09B0272-0700
2. The timer synchro register (TSNC) sets the synchronization.
Bit 3:
CKEG0
0
1
—
Bit 5:
CCLR0
0
1
0
1
compare match. When functioning as an input capture register, TCNT is cleared upon
input capture.
Description
TCNT is not cleared
TCNT is cleared by general register A (GRA) compare match or input
capture *
TCNT is cleared by general register B (GRB) compare match or input
capture *
Synchronizing clear: TCNT is cleared in synchronization with clear of other
timer counters operating in sync *
Description
Count rising edges
Count falling edges
Count both rising and falling edges
1
1
2
(Initial value)
(Initial value)