HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 240

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Interrupt Controller (INTC)
Bit 13: BLMSK Description
0
1
Bit 12—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 11 and 10—IRQ5 Sense Select (IRQ51S and IRQ50S): Select whether the interrupt signal
to the IRQ5 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
1
Bits 9 and 8—IRQ4 Sense Select (IRQ41S and IRQ40S): Select whether the interrupt signal to
the IRQ4 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 9: IRQ41S
0
1
Bits 7 and 6—IRQ3 Sense Select (IRQ31S and IRQ30S): Select whether the interrupt signal to
the IRQ3 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 7: IRQ31S
0
1
Rev.6.00 Mar. 27, 2009 Page 182 of 1036
REJ09B0254-0600
NMI interrupts are masked when the BL bit is 1
NMI interrupts are accepted regardless of the BL bit setting
0
1
0
1
Bit 8: IRQ40S
0
1
0
1
Bit 6: IRQ30S
0
1
0
1
An interrupt request is detected at IRQ5 input falling edge
An interrupt request is detected at IRQ5 input rising edge
An interrupt request is detected at IRQ5 input low level
Reserved
Description
An interrupt request is detected at IRQ4 input falling edge
An interrupt request is detected at IRQ4 input rising edge
An interrupt request is detected at IRQ4 input low level
Reserved
Description
An interrupt request is detected at IRQ3 input falling edge
An interrupt request is detected at IRQ3 input rising edge
An interrupt request is detected at IRQ3 input low level
Reserved
(Initial value)
(Initial value)
(Initial value)
(Initial value)