HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 328

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 On-Chip Oscillation Circuits
10.5
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of
these are controlled by software through the frequency control register. The methods are described
below.
10.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC2, STC1 and STC0 bits. The division ratio can also be set in
4. The processor pauses internally and the WDT starts incrementing. In clock modes 0 to 2 and 7,
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
10.5.2
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC2 to IFC0 = 000 and PFC2 to PFC0 = 010.
2. Set the IFC2, IFC1, IFC0, PFC2, PFC1, and PFC0 bits to the new division ratio. The values
3. The clock is immediately supplied at the new division ratio.
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WDT. The following must be set:
WTCSR register TME bit = 0: WDT stops
WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock
WTCNT counter: Initial counter value
the IFC2 to IFC0 bits and PFC2 to PFC0 bits.
the internal and peripheral clocks both stop.
operating again. The WDT stops after it overflows.
that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note
that if the wrong value is set, the processor will malfunction.
Changing the Multiplication Rate
Changing the Division Ratio
Changing the Frequency