HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 845

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 7, 3, and 2—Reserved
Bits 15 to 12—LCDC Power-On Sequence Period (ONC): Set the period from VEPWC
assertion to DON assertion in the power-on sequence of the LCD module in frame units.
This period is the (c) period in figures 25.4 to 25.7. For details on setting this register, see table
25.4. (The setting method is common for ONC, ONA, ONB, OFFD, OFFE, and OFFF.) 1 is to be
subtracted from the setting.
Bits 11 to 8—LCDC Power-Off Sequence Period (OFFD): Set the period from DON negation
to VEPWC negation in the power-off sequence of the LCD module in frame units.
This period is the (d) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
Bit 6—VCPWC Pin Enable (VCPE): Sets whether or not to enable a power-supply control
sequence using the VCPWC pin.
Bit 6
VCPE
0
1
Bit 5—VEPWC Pin Enable (VEPE): Sets whether or not to enable a power-supply control
sequence using the VEPWC pin.
Bit 5
VEPE
0
1
Bit 4—DON Pin Enable (DONE): Sets whether or not to enable a power-supply control
sequence using the DON pin.
Bit 4
DONE
0
1
Description
power-off sequence
Description
power-off sequence
Description
off sequence
Disabled: VCPWC pin is masked and fixed low
Enabled: VCPWC pin output is asserted and negated according to the power-on or
Disabled: VEPWC pin is masked and fixed low
Enabled: VEPWC pin output is asserted and negated according to the power-on or
Disabled: DON pin is masked and fixed low
Enabled: DON pin output is asserted and negated according to the power-on or power-
Rev.6.00 Mar. 27, 2009 Page 787 of 1036
Section 25 LCD Controller
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)