HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 35

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 I/O Ports
27.1 Overview........................................................................................................................... 845
27.2 Register Configuration...................................................................................................... 846
27.3 Ports A to C, E, J, K.......................................................................................................... 847
27.4 Port D................................................................................................................................ 848
27.5 Ports F, M ......................................................................................................................... 850
27.6 Port G................................................................................................................................ 851
27.7 Port H................................................................................................................................ 852
27.8 Port L ................................................................................................................................ 854
27.9 SC Port.............................................................................................................................. 855
Section 28 A/D Converter
28.1 Overview........................................................................................................................... 857
28.2 Register Descriptions ........................................................................................................ 861
28.3 Bus Master Interface ......................................................................................................... 865
28.4 Operation........................................................................................................................... 867
26.3.6 Port F Control Register (PFCR)........................................................................... 832
26.3.7 Port G Control Register (PGCR) ......................................................................... 833
26.3.8 Port H Control Register (PHCR) ......................................................................... 835
26.3.9 Port J Control Register (PJCR) ............................................................................ 836
26.3.10 Port K Control Register (PKCR) ......................................................................... 837
26.3.11 Port L Control Register (PLCR) .......................................................................... 838
26.3.12 Port M Control Register (PMCR) ........................................................................ 839
26.3.13 SC Port Control Register (SCPCR) ..................................................................... 840
27.3.1 Ports A to C, E, J, K Data Rgister
27.4.1 Port D Data Register (PDDR).............................................................................. 848
27.5.1 Ports F, M Data Register (PFDR, PMDR)........................................................... 850
27.6.1 Port G Data Register (PGDR).............................................................................. 851
27.7.1 Port H Data Register (PHDR).............................................................................. 852
27.8.1 Port L Data Register (PLDR)............................................................................... 854
27.9.1 Port SC Data Register (SCPDR).......................................................................... 855
28.1.1 Features................................................................................................................ 857
28.1.2 Block Diagram..................................................................................................... 858
28.1.3 Input Pins ............................................................................................................. 859
28.1.4 Register Configuration......................................................................................... 860
28.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 861
28.2.2 A/D Control/Status Register (ADCSR) ............................................................... 862
28.2.3 A/D Control Register (ADCR) ............................................................................ 864
28.4.1 Single Mode (MULTI = 0) .................................................................................. 867
(PADR, PBDR, PCDR, PEDR, PJDR, PKDR) ................................................... 847
............................................................................................................ 845
................................................................................................. 857
Rev.6.00 Mar. 27, 2009 Page xxxiii of lvi
REJ09B0254-0600