HD6417727F100V Renesas Electronics America, HD6417727F100V Datasheet - Page 357

• Manufacturer Part Number: HD6417727F100V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 2n + 1, 2n—Area n (6 to 2, 0) Intercycle Idle Specification (AnIW1, AnIW0): Specify the
number of idles inserted between bus cycles when switching between physical space area n (6 to
2, 0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1: AnIW1
0
1
12.2.4
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Initial value:
R/W: R/W
Bit:
Wait State Control Register 2 (WCR2)
W2
A6
15
1
R/W
W1
A6
14
1
Bit 2n: AnIW0
0
1
0
1
R/W
W0
A6
13
1
R/W
W2
A5
12
1
R/W
W1
A5
11
1
R/W
W0
A5
10
1
Description
1 idle cycle inserted
1 idle cycle inserted
2 idle cycles inserted
3 idle cycles inserted (Initial value)
R/W
W2
A4
9
1
R/W
W1
A4
8
1
Rev.6.00 Mar. 27, 2009 Page 299 of 1036
R/W
W0
A4
7
1
Section 12 Bus State Controller (BSC)
R/W
W1
A3
6
1
R/W
W0
A3
5
1
R/W
W1
A2
4
1
R/W
W0
A2
3
1
REJ09B0254-0600
R/W
W2
A0
2
1
R/W
W1
A0
1
1
R/W
W0
A0
0
1