HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 185

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.5
3.5.1
The SH-4 supports the following MMU functions.
1. The MMU decodes the virtual address to be accessed by software, and performs address
2. The MMU determines the cache access status on the basis of the page management
3. If address translation cannot be performed normally in a data access or instruction access, the
4. If address translation information is not recorded in the ITLB in an instruction access, the
3.5.2
Software processing for the MMU consists of the following:
1. Setting of MMU-related registers. Some registers are also partially updated by hardware
2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB
3. MMU exception handling. When an MMU exception occurs, processing is performed based on
3.5.3
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB
instruction is issued, the SH-4 copies the contents of PTEH, PTEL, and PTEA to the UTLB entry
indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and
therefore address translation information purged from the UTLB entry may still remain in the
ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is
translation by controlling the UTLB/ITLB in accordance with the MMUCR settings.
information read during address translation (C, WT, SA, and TC bits).
MMU notifies software by means of an MMU exception.
MMU searches the UTLB, and if the necessary address translation information is recorded in
the UTLB, the MMU copies this information into the ITLB in accordance with
MMUCR.LRUI.
automatically.
entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB.
ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For
deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped
UTLB/ITLB.
information set by hardware.
MMU Functions
MMU Hardware Management
MMU Software Management
MMU Instruction (LDTLB)
Rev.4.00 Oct. 10, 2008 Page 85 of 1122
3. Memory Management Unit (MMU)
REJ09B0370-0400