HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 637
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4. Burst Mode, Dual Address Mode, Edge Detection
5. Burst Mode, Single Address Mode, Edge Detection
Suspension of DMA Transfer in Case of DREQ Level Detection
With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can judge from the
rising edge of CKIO that DRAK has been asserted, and can suspend DMA transfer by negating
DREQ. In this case, the next DRAK signal is not output.
In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles
after the first sampling operation, and the second sampling operation begins one cycle after the
start of the first DMAC transfer bus cycle.
In single address mode, the DACK signal is output every DMAC transfer cycle.
In figure 14.22, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
In burst mode using dual address mode and edge detection, DREQ sampling is performed in
the first cycle only.
For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
In burst mode using single address mode and edge detection, DREQ sampling is performed
only in the first cycle.
For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 537 of 1122
REJ09B0370-0400
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