HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 483

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is
performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS-
before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using
the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is
issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When
the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous
DRAM, after waiting for the end of any currently executing external bus cycle. All refresh
requests for memory in the self-refresh state are ignored.
Bit 1: RMODE
0
1
Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when
using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of
memory other than DRAM. Set this bit to 1 only when DRAM is used.
13.2.9
The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the OE
and WE signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6.
The OE and WE signal assertion width is set by the wait control bits in the WCR2 register.
PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Initial value:
Initial value:
Bit name: A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2
Bit name: A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0
R/W:
R/W:
PCMCIA Control Register (PCR)
Bit:
Bit:
R/W
R/W
15
0
7
0
Description
CAS-before-RAS refreshing is performed (when RFSH = 1)
Self-refreshing is performed (when RFSH = 1)
R/W
R/W
14
0
6
0
R/W
R/W
13
0
0
5
R/W
R/W
12
0
4
0
Rev.4.00 Oct. 10, 2008 Page 383 of 1122
R/W
R/W
11
0
3
0
13. Bus State Controller (BSC)
R/W
R/W
10
0
2
0
REJ09B0370-0400
R/W
R/W
9
0
1
0
(Initial value)
R/W
R/W
8
0
0
0

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