HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 890

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19. Interrupt Controller (INTC)
19.5
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 19.8.
Table 19.8 Interrupt Response Time
Item
Time for priority decision and
SR mask bit comparison*
Wait time until end of
sequence being executed by
CPU
Time from interrupt exception
handling (save of SR and PC)
until fetch of first instruction of
exception handler is started
Response
time
Legend:
Icyc:
Bcyc: One CKIO cycle
S:
Note:
Rev.4.00 Oct. 10, 2008 Page 790 of 1122
REJ09B0370-0400
One cycle of internal clock supplied to CPU, etc.
Latency of instruction
*
Interrupt Response Time
In the SH7751, this includes the case where the mask bit (IMASK) in SR is changed
and a new interrupt is generated.
Total
Minimum
case
Maximum
case
NMI
1Icyc + 4Bcyc
S – 1 (≥ 0) ×
Icyc
4 × Icyc
5Icyc + 4Bcyc
+ (S – 1)Icyc
13Icyc
36 + S Icyc
Number of States
RL
1Icyc + 7Bcyc
S – 1 (≥ 0) ×
Icyc
4 × Icyc
5Icyc + 7Bcyc
+ (S – 1)Icyc
19Icyc
60 + S Icyc
Peripheral
Modules
1Icyc + 2Bcyc
S – 1 (≥ 0) ×
Icyc
4 × Icyc
5Icyc + 2Bcyc
+ (S – 1)Icyc
9Icyc
20 + S Icyc
Notes
When Icyc:
Bcyc = 2:1
When Icyc:
Bcyc = 8:1

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