HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 292

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7. Instruction Set
Addressing
Mode
Register
indirect with
displacement
Indexed
register
indirect
GBR indirect
with
displacement
Indexed
GBR indirect
Rev.4.00 Oct. 10, 2008 Page 192 of 1122
REJ09B0370-0400
Instruction
Format
@(disp:4, Rn) Effective address is register Rn contents with
@(R0, Rn)
@(disp:8,
GBR)
@(R0, GBR)
Effective Address Calculation Method
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Effective address is sum of register Rn and R0
contents.
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Effective address is sum of register GBR and R0
contents.
(zero-extended)
(zero-extended)
GBR
1/2/4
GBR
1/2/4
disp
disp
Rn
R0
R0
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
+ disp × 1/2/4
GBR + R0
Rn + R0
GBR
Calculation
Formula
Byte: Rn +
disp → EA
Word: Rn +
disp × 2 → EA
Longword:
Rn + disp × 4
→ EA
Rn + R0 → EA
Byte: GBR +
disp → EA
Word: GBR +
disp × 2 → EA
Longword:
GBR + disp ×
4 → EA
GBR + R0 →
EA

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