HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 280

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6. Floating-Point Unit
• Flag: FPU exception flag field
• RM: Rounding mode
• Bits 22 to 31: Reserved
6.3.3
Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL
register is a system register, and is accessed from the CPU side by means of LDS and STS
instructions. For example, to convert the integer stored in general register R1 to a single-precision
floating-point number, the processing flow is as follows:
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These bits are always read as 0, and should only be written with 0.
When an FPU operation instruction is executed, the FPU exception cause field is cleared to
zero first. When the next FPU exception is occurred, the corresponding bits in the FPU
exception cause field and FPU exception flag field are set to 1. The FPU exception flag field
holds the status of the exception generated after the field was last cleared.
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Cause
Enable
Flag
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Floating-Point Communication Register (FPUL)
FPU exception
cause field
FPU exception
enable field
FPU exception
flag field
FPU
Error (E)
Bit 17
None
None
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
Overflow
(O)
Bit 14
Bit 9
Bit 4
Underflow
(U)
Bit 13
Bit 8
Bit 3
Inexact
(I)
Bit 12
Bit 7
Bit 2