HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 516

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
Wait State Control: As the clock frequency increases, it becomes impossible to complete all
states in one cycle as in basic access. Therefore, provision is made for state extension by using the
setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in
figure 13.15. Additional Tpc cycles (cycles used to secure the RAS precharge time) can be
inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from
RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of
the RCD bit in MCR. Also, the number of cycles from CAS assertion to the end of the access can
be varied between 1 and 16 according to the setting of A3W2 to A3W0 in WCR2.
Rev.4.00 Oct. 10, 2008 Page 416 of 1122
REJ09B0370-0400
CKIO
Address
CSn
RD/WR
RAS
CASn
D31–D0
(read)
D31–D0
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Tr1
Figure 13.15 DRAM Wait State Timing
Tr2
Row
Trw
Tc1
Tcw
Column
Tc2
Tpc
Tpc