HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 238

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5. Exceptions
5.2
There are three registers related to exception handling. Addresses are allocated for these, and can
be accessed by specifying the P4 address or area 7 address.
1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12-
2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 14-
3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit
The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1.
Rev.4.00 Oct. 10, 2008 Page 138 of 1122
REJ09B0370-0400
bit exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception is accepted.
EXPEVT can also be modified by software.
bit exception code. The exception code set in INTEVT is that for an interrupt request. The
exception code is set automatically by hardware when an exception is accepted. INTEVT can
also be modified by software.
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
EXPEVT
31
INTEVT
31
TRA
31
Legend:
0:
imm:
0
0
0
Register Descriptions
Reserved bits. These bits are always read as 0, and should only be written
with 0.
8-bit immediate data of the TRAPA instruction
Figure 5.1 Register Bit Configurations
14 13
0
12 11
0
10 9
0
Exception code
Exception code
imm
2
1 0
0 0
0
0