UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 273

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the
Capture & count clear input
TI000 pin valid edge input)
Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of
TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00
is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected. Therefore,
a cycle is stored in CR010 if TM00 does not overflow.
If an overflow occurs, take the value that results from adding 10000H to the value stored in CR010 as a cycle.
Clear bit 0 (OVF00) of 16-bit timer mode control register 00 (TMC00) to 0.
<1> Pulse cycle =
<2> High-level pulse width = (10000H
<3> Low-level pulse width = (Pulse cycle
Capture trigger input
(TMC003, TMC002)
Capture interrupt
Capture interrupt
Capture register
Capture register
TM00 register
Operable bits
Overflow flag
(INTTM010)
(INTTM000)
(CR000)
(CR010)
(OVF00)
(TI000)
(TI010)
FFFFH
0000H
Figure 6-50. Timing Example of Pulse Width Measurement (3)
00
L
L
0000H
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(10000H
Count clock cycle
Count clock cycle
TMC00 = 08H, PRM00 = 10H, CRC00 = 07H
10
M
Preliminary User’s Manual U19111EJ2V1UD
<2>
A
Number of times OVF00 bit is set to 1 + Captured value of CR010)
Number of times OVF00 bit is set to 1 + Captured value of CR000)
M
<1>
<3>
High-level pulse width)
N
A
<2>
<1>
N
B
<3>
S
0 write clear
B
<2>
<1>
S
C
<3>
P
C
<2>
<1>
P
D
<3>
Q
D
Q
00
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