UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 631

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(b) When LVI default start function enabled is set (LVISTART = 1)
Figure 22-6 shows the timing of the internal reset signal generated by the low-voltage detector.
Caution Even when the LVI default start function is used, if it is set to LVI operation prohibition by
Start in the following initial setting state.
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
When starting operation
When stopping operation
Either of the following procedures must be executed.
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (V
V
Set the low-voltage detection level selection register (LVIS) to 0FH (V
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
Set bit 0 (LVIF) of LVIM to 0 (“Supply voltage (V
Write 00H to LVIM.
Clear LVIMD to 0 and then LVION to 0.
DDLVI
(LVI default start detection voltage) = 1.91 V 0.1 V
the software (LVION (bit 7 of LVIM register) = 0), it operates as follows:
This is due to the fact that while the pulse width detected by LVI must be 200 s max.,
Does not perform low-voltage detection during LVION = 0.
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
CHAPTER 22 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U19111EJ2V1UD
DD
)
detection voltage (V
LVI
= 1.91 V 0.1 V ).
LVI
)”)
DD
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