UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 455

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address: FFA7H
IICACTL0
Symbol
Notes 1. The IICAS0 register, the STCF and IICBSY bits of the IICAF0 register, and the CLD0 and
Caution The start condition is detected immediately after I
WREL0
Be sure to set this bit (1) while the SCLA0 and SDLA0 lines are at high level.
Condition for clearing (IICE0 = 0)
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
Condition for clearing (LREL0 = 0)
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 =
1), the SDAA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
LREL0
Cleared by instruction
Reset
After a stop condition is detected, restart is in master mode.
An address match or extension code reception occurs after the start condition.
Automatically cleared after execution
Reset
Automatically cleared after execution
Reset
IICE0
IICE0
<7>
0
1
0
1
0
1
Note 2
2. The signal of this bit is invalid while IICE0 is 0.
Note 2
After reset: 00H
while the SCLA0 line is at high level and the SDAA0 line is at low level. Immediately after
enabling I
instruction.
DAD0 bits of the IICACTL1 register are reset.
Stop operation. Reset the IICA status register 0 (IICAS0)
Enable operation.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLA0 and SDAA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICACTL0) and IICA status register 0 (IICAS0) are cleared
to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (1/4)
LREL0
<6>
2
C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation
WREL0
<5>
R/W
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
SPIE0
<4>
WTIM0
Exit from communications
<3>
I
2
C operation enable
Wait cancellation
Condition for setting (IICE0 = 1)
Condition for setting (LREL0 = 1)
Condition for setting (WREL0 = 1)
Set by instruction
Set by instruction
Set by instruction
ACKE0
<2>
Note 1
. Stop internal operation.
2
C is enabled to operate (IICE0 = 1)
STT0
<1>
SPT0
<0>
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