UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 619

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(2) When LVI is ON upon power application (option byte: LVISTART = 1)
V
V
V
POR
PDR
LVI
(when X1 oscillation
oscillation clock (f
Internal high-speed
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
Remark V
Internal reset signal
= 1.91 V (TYP.)
= 1.61 V (TYP.)
= 1.59 V (TYP.)
system clock (f
CPU
Supply voltage
High-speed
is selected)
1.8 V
2.
3.
4.
5.
Operation
(V
LOW-VOLTAGE DETECTOR).
V
V
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
XH
V
Note 3
Note 1
Note 3
Note 3
IH
stops
0 V
DD
)
)
LVI
The operation guaranteed range is 1.8 V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
The internal high-speed oscillation clock, high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation
stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the
stabilization time.
These are preliminary values and subject to change.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and
starting normal operation.
LVI
POR
PDR
)
When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is less than 5.8 ms:
A POC processing time of about 2.2 to 6.0 ms is required between reaching 1.59 V (TYP.) and
starting normal operation.
When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is greater than 5.8 ms:
A reset processing time of about 125 to 153 s is required between reaching 1.91 V (TYP.) and
starting normal operation.
:
: POC power supply rise detection voltage
: POC power supply fall detection voltage
LVI detection voltage
Wait for oscillation
accuracy stabilization
Note 5
POC processing time
Reset processing time
oscillation clock)
(internal high-speed
(V
reset (default)
Normal operation
to be used for
LVI
Set LVI
specified by software
Starting oscillation is
= 1.91 V)
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Note 4
Preliminary User’s Manual U19111EJ2V1UD
and Low-Voltage Detector (2/2)
Note 2
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
Reset processing time
used for interrupt
Set LVI to be
V
DD
oscillation clock)
(internal high-speed
Normal operation
specified by software
Starting oscillation is
5.5 V. To make the state at lower than 1.8 V reset
Note 4
Note 2
(oscillation
Reset
period
stop)
Note 5
(V
to be used for
reset (default)
Wait for oscillation
accuracy stabilization
LVI
Set LVI
= 1.91 V)
oscillation clock)
(internal high-speed
POC processing time
Normal operation
Reset processing time
specified by software
Starting oscillation is
voltage (V
Change LVI
detection
Note 4
Note 2
LVI
)
Operation stops
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