UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 222

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(5) Main OSC control register (MOC)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU
operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Address: FFA2H
Symbol
MOC
Cautions 1. Clear MSTOP to 0 while the regulator mode control register (RMC) is 00H.
MSTOP
MSTOP
<7>
0
1
After reset: 80H
2. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
3. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
4. The peripheral hardware cannot operate when the peripheral hardware clock is
other than the high-speed system clock.
following conditions.
<1> 78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L
<2> 78K0/KC2-L
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
register (OSCCTL) is 0 (input port mode).
stopped. To resume the operation of the peripheral hardware after the peripheral
hardware clock has been stopped, initialize the peripheral hardware.
Figure 5-8. Format of Main OSC Control Register (MOC)
X1 oscillator operating
X1 oscillator stopped
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
• When CLS = 1 (when CPU operates with the subsystem clock)
6
0
clock)
clock)
R/W
X1 oscillation mode
5
0
Control of high-speed system clock operation
4
0
3
0
External clock from EXCLK pin is enabled
External clock from EXCLK pin is disabled
CHAPTER 5 CLOCK GENERATOR
Specifically, set under either of the
External clock input mode
2
0
1
0
0
0
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