UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 513

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(3) IICA flag register 0 (IICAF0)
This register sets the operation mode of I
This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag (STCF)
and I
The IICRSV bit can be used to enable/disable the communication reservation function.
The STCEN bit can be used to set the initial value of the IICBSY bit.
The IICRSV and STCEN bits can be written only when the operation of I
control register 0 (IICACTL0) = 0). When operation is enabled, the IICAF0 register can be read.
Reset signal generation clears this register to 00H.
2
C bus status flag (IICBSY) are read-only.
Remark
Condition for clearing (ACKD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
• Reset
Condition for clearing (STD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
• Reset
Condition for clearing (SPD0 = 0)
• At the rising edge of the address transfer byte’s first
• When the IICE0 bit changes from 1 to 0 (operation
• Reset
ACKD0
stop)
following address transfer
stop)
clock following setting of this bit and detection of a
start condition
stop)
SPD0
STD0
0
1
0
1
0
1
LREL0: Bit 6 of IICA control register 0 (IICACTL0)
IICE0:
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Figure 15-6. Format of IICA Status Register 0 (IICAS0) (3/3)
Bit 7 of IICA control register 0 (IICACTL0)
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD0 = 1)
• After the SDAA0 line is set to low level at the rising
Condition for setting (STD0 = 1)
• When a start condition is detected
Condition for setting (SPD0 = 1)
• When a stop condition is detected
edge of SCLA0’s ninth clock
CHAPTER 15 SERIAL INTERFACE IICA
2
2
C is disabled (bit 7 (IICE0) of the IICA
C bus.
499