UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 535

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
15.5.14 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is
not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT0) of the IICACTL0 register is set to 1 while the bus is not used (after a stop condition is detected), a
start condition is automatically generated and wait state is set.
If an address is written to the IICA shift register (IICA) after bit 4 (SPIE0) of the IICACTL0 register was set to 1, and
it was detected by generation of an interrupt request signal (INTIICA0) that the bus was released (detection of the
stop condition), then the device automatically starts communication as the master. Data written to the IICA register
before the stop condition is detected is invalid.
When the STT0 bit has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using the MSTS0 bit (bit 7 of the IICA status
register 0 (IICAS0)) after the STT0 bit is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
released by setting bit 6 (LREL0) of IICA control register 0 (IICACTL0) to 1 and saving communication).
Remark IICWL: IICA low-level width setting register
Wait time from setting STT0 = 1 to checking the MSTS0 flag:
(IICWL setting value + IICWH setting value + 4) + t
IICWH: IICA high-level width setting register
t
f
F
PRS
:
:
SDAA0 and SCLA0 signal falling times
(refer to CHAPTER 28 ELECTRICAL SPECIFICATIONS)
Peripheral hardware clock frequency
F
× 2 × f
PRS
CHAPTER 15 SERIAL INTERFACE IICA
[clocks]
521