UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 740

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
16-bit data
transfer
8-bit
operation
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
4.
2.
3.
MOVW
XCHW
ADD
ADDC
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Only when rp = BC, DE or HL
Except “r = A”
register (PCC).
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
Note 3
Note 3
Note 4
Note 4
Bytes
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
−
6
6
−
−
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
10
10
12
12
−
8
8
8
8
−
−
−
−
8
−
−
5
9
5
9
9
9
−
8
−
−
5
9
5
9
9
9
(saddrp) ← word
(saddrp) ← AX
(addr16) ← AX
rp ← word
sfrp ← word
AX ← (saddrp)
AX ← sfrp
sfrp ← AX
AX ← rp
rp ← AX
AX ← (addr16)
AX ↔ rp
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
r, CY ← r + A
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + (HL + B)
A, CY ← A + (HL + C)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
r, CY ← r + A + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + C
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A + (HL + B) + CY
A, CY ← A + (HL + C) + CY
CPU
) selected by the processor clock control
CHAPTER 27 INSTRUCTION SET
Operation
Z AC CY
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