UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 542

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(2) Master operation in multi-master system
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of
one frame). If the SDAA0 pin is constantly at low level, decide whether to release the I
SDAA0 pins = high level) in conformance with the specifications of the product that is communicating.
1
No
ACKE0 = WTIM0 = SPIE0 = 1
Setting STCEN and IICRSV
IICACTL0
IICACTL0
Checking bus status
IICWL, IICWH
Enables reserving
interrupt occurs?
Master operation
communication.
IICAF0
SVA0
IICRSV = 0?
Setting port
Setting port
SPD0 = 1?
SPIE0 = 1
IICE0 = 1
INTIICA0
START
starts?
A
0XX111XXB
1XX111XXB
Yes
Yes
Yes
Yes
(Communication start request)
XXH
0XH
Bus status is
being checked.
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Figure 15-30. Master Operation in Multi-Master System (1/3)
XXH
Note
Disables reserving
communication.
(No communication start request)
No
No
No
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)).
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Releases the bus for a specific period.
Slave operation
Set the port from input mode to output mode and enable the output of the I
(see 15.3 (9) Port mode register 6 (PM6)).
B
STCEN = 1?
interrupt occurs?
Yes
Slave operation
SPIE0 = 0
INTIICA0
Yes
No
Waits for a communication request.
No
CHAPTER 15 SERIAL INTERFACE IICA
interrupt occurs?
SPD0 = 1?
SPT0 = 1
INTIICA0
Yes
Yes
2
C bus
No
No
Waits for detection
of the stop condition.
Prepares for starting
communication
(generates a stop condition).
Slave operation
2
C bus (SCLA0 and
528