UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 481

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Remark T
R
(g) Noise filter of receive data
(h) SBF transmission
X
D6/P14
INTST6
The RxD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as input
data.
Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation is
delayed by two clocks from the external signal status.
When the device is use in LIN communication operation, the SBF (Synchronous Break Field) transmission control
function is used for transmission. For the transmission operation of LIN, see Figure 15-1 LIN Transmission
Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the T
high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered, and SBF
transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6 (ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following the
end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and SBTT6 is
automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6), or
until SBTT6 is set to 1.
SBTT6
T
Base clock
X
D6
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
X
D6:
T
X
D6 pin (output)
1
2
In
3
Figure 15-21. Noise Filter Circuit
Figure 15-22. SBF Transmission
4
Q
5
6
Internal signal A
Match detector
7
8
CHAPTER 15 SERIAL INTERFACE UART6
9
10
11
In
LD_EN
12
13
Q
Stop
Internal signal B
X
D6 pin outputs
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