UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 702

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(3) Port mode register 12 (PM12)
25.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM).
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time,
the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM12 to FFH.
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
when V
(TYP.)), generates an internal reset signal when EXLVI < V
(V
(TYP.)). When EXLVI drops lower than V
V
EXLVI
DD
Address: FF2CH
Symbol
PM12
< V
), generates an interrupt signal (INTLVI).
DD
LVISEL: Bit 2 of LVIM
LVI
Remark The format of port mode register 12 of 78K0/KB2 products is different from the above
< V
) or when V
PM12n
LVI
0
1
, and releases internal reset when V
7
1
format. See 5.3 Registers Controlling Port Function (1) Port mode registers
(PMxx).
After reset: FFH
DD
Output mode (output buffer on)
Input mode (output buffer off)
becomes V
Figure 25-4. Format of Port Mode Register 12 (PM12)
6
1
LVI
R/W
or higher (V
5
1
EXLVI
P12n pin I/O mode selection (n = 0 to 4)
(EXLVI < V
DD
DD
PM124
) and detection voltage (V
) and detection voltage (V
DD
4
DD
≥ V
≥ V
LVI
LVI
EXLVI
EXLVI
), generates an interrupt signal (INTLVI).
.
PM123
) or when EXLVI becomes V
, and releases internal reset when EXLVI ≥ V
CHAPTER 25 LOW-VOLTAGE DETECTOR
3
PM122
2
LVI
LVI
), generates an internal reset signal
). When V
PM121
1
DD
EXLVI
drops lower than V
PM120
or higher (EXLVI ≥
0
EXLVI
EXLVI
= 1.21 V
= 1.21 V
EXLVI
702
.
LVI